On Friday, August 21, 2015 at 12:25:54 AM, vikas wrote:
> Hi,
Hi,
> On 08/20/2015 02:56 PM, Marek Vasut wrote:
> > On Thursday, August 20, 2015 at 06:48:36 PM, vikas wrote:
> >> Hi,
> >>
> >> On 08/19/2015 08:54 PM, Marek Vasut wrote:
> >>> On Saturday, August 15, 2015 at 04:15:59 AM, Vikas Mano
Hi,
On 08/20/2015 02:56 PM, Marek Vasut wrote:
> On Thursday, August 20, 2015 at 06:48:36 PM, vikas wrote:
>> Hi,
>>
>> On 08/19/2015 08:54 PM, Marek Vasut wrote:
>>> On Saturday, August 15, 2015 at 04:15:59 AM, Vikas Manocha wrote:
This patch is to separate the base trigger from the read/wri
On Thursday, August 20, 2015 at 06:48:36 PM, vikas wrote:
> Hi,
>
> On 08/19/2015 08:54 PM, Marek Vasut wrote:
> > On Saturday, August 15, 2015 at 04:15:59 AM, Vikas Manocha wrote:
> >> This patch is to separate the base trigger from the read/write transfer
> >> start addresses.
> >>
> >> Base tr
Hi,
On 08/19/2015 08:54 PM, Marek Vasut wrote:
> On Saturday, August 15, 2015 at 04:15:59 AM, Vikas Manocha wrote:
>> This patch is to separate the base trigger from the read/write transfer
>> start addresses.
>>
>> Base trigger register address (0x1c register) corresponds to the address
>> which
On Saturday, August 15, 2015 at 04:15:59 AM, Vikas Manocha wrote:
> This patch is to separate the base trigger from the read/write transfer
> start addresses.
>
> Base trigger register address (0x1c register) corresponds to the address
> which should be put on AHB bus to handle indirect transfer t
This patch is to separate the base trigger from the read/write transfer start
addresses.
Base trigger register address (0x1c register) corresponds to the address which
should be put on AHB bus to handle indirect transfer triggered before.
To handle indirect transfer we need to issue addresses fro
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