Maybe I'm confusing DDR controller with SPD eeprom. My board have 2 SPDs in
0x51 and 0x53, one for each DIMM. I tought that I should set 2 DDR
controllers to fsl_ddr_get_spd() takes the information of them in
cpu/mpc8xxx/ddr/main.c.
for (i = 0; i CONFIG_NUM_DDR_CONTROLLERS; i++) {
Thanks for the advice. I'll try to set the correct configurations and adjust
my ddr.c.
On Fri, May 15, 2009 at 10:56 AM, Werner Nedel wmne...@gmail.com wrote:
Maybe I'm confusing DDR controller with SPD eeprom. My board have 2 SPDs in
0x51 and 0x53, one for each DIMM. I tought that I should
Hi,
I'm working on a mpc85xx board very similar to MPC8548CDS. I have 2 DIMMs
and each one with it own spd eeprom and with only one chip select (cs0 and
cs2). I'm trying to use two 1Gb DDR2s. My ddr configurations:
/* DDR Setup */
#define CONFIG_VERY_BIG_RAM
#define CONFIG_FSL_DDR2
#undef
The tlb settings looks fine (debbug in setup_ddr_tlbs()):
ram_tlb_address: 0x0, ram_tlb_address: 0x0, ram_tlb_index: 0x8, tlb_size:
0xa
ram_tlb_address: 0x4000, ram_tlb_address: 0x4000, ram_tlb_index:
0x9, tlb_size: 0xa
tlb_size: 0xa is _not_ fine.
Quoting the 8540 reference manual:
Interesting. I've tried to use your patch but still hanging board_init_f.
Even putting BOOKE_PAGESZ_256M in set_tlb the problem occur.
On Thu, May 14, 2009 at 2:49 PM, Fredrik Arnerup
fredrik.arne...@edgeware.tv wrote:
The tlb settings looks fine (debbug in setup_ddr_tlbs()):
I'm working on a mpc85xx board very similar to MPC8548CDS. I
have 2 DIMMs and each one with it own spd eeprom and with
only one chip select (cs0 and cs2). I'm trying to use two 1Gb
DDR2s. My ddr configurations:
/* DDR Setup */
#define CONFIG_VERY_BIG_RAM
#define CONFIG_FSL_DDR2
#undef
The tlb settings looks fine (debbug in setup_ddr_tlbs()):
ram_tlb_address: 0x0, ram_tlb_address: 0x0, ram_tlb_index:
0x8, tlb_size:
0xa
ram_tlb_address: 0x4000, ram_tlb_address: 0x4000,
ram_tlb_index:
0x9, tlb_size: 0xa
tlb_size: 0xa is _not_ fine.
No, TLB_SIZE = 0xa
Interesting. I've tried to use your patch but still hanging
board_init_f.
Even putting BOOKE_PAGESZ_256M in set_tlb the problem occur.
Because you are using the 8548 with e500v2 core, so the bug doesn't
effect your board when you are using the 1G DIMMs.
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