Hi I'm trying to adjust u-boot to our board which is using a P2020. I'm having strange effects with the stack in the L1 data cache, during the NAND phase as well as in the SPL main u-boot.
Sometimes when a value is written to the cache this value itself shows up correctly. However it's possible that other values in the same cache line may change as well. When these values are read back (e.g. LR) anything can go wrong. I don't attribute this to u-boot itself but maybe somebody has an idea what could be wrong to get these strange effects. It's also possible that the JTAG debugger has an influence, but even without the booting is unreliable. Sometimes it comes up without a problem, sometimes it hangs even in the middle of outputting a string on the SIO. As we have two boards with the same behaviour I don't suspect a hardware defect but a problem in either system (layout, power supply) or "hard-software" (FPGA). Thanks and sorry for the off topic mail. If somebody has an idea we can continue this in private mail. bye Fabi _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
