On Feb 11, 2011, at 8:34 AM, Fabian Cenedese wrote:
2. Why does the cache to be cleared at all? L2-SRAM is usually
just used to copy in the second part of the u-boot image, so
the 0s will be overwritten again anyway.
This needs to be done because we enable ECC.
I'm still trying to get
2. Why does the cache to be cleared at all? L2-SRAM is usually
just used to copy in the second part of the u-boot image, so
the 0s will be overwritten again anyway.
This needs to be done because we enable ECC.
I'm still trying to get my head around this. From looking at the code
this doesn't
I'm creating a SPL u-boot image for our board. In the file
arch/powerpc/cpu/mpc85xx/cpu_init_nand.c is the setup for
the L2 cache as SRAM. In the end is a loop that fills the
cache with 0 (512KB in this case).
1. Why is the access byte-wise and not dword-wise? This
is only for mpc85xx and
On Feb 9, 2011, at 2:06 AM, Fabian Cenedese wrote:
I'm creating a SPL u-boot image for our board. In the file
arch/powerpc/cpu/mpc85xx/cpu_init_nand.c is the setup for
the L2 cache as SRAM. In the end is a loop that fills the
cache with 0 (512KB in this case).
1. Why is the access
On Feb 7, 2011, at 4:22 AM, Fabian Cenedese wrote:
At 14:17 03.02.2011 +0100, Fabian Cenedese wrote:
Hi
I'm creating a SPL u-boot image for our board. In the file
arch/powerpc/cpu/mpc85xx/cpu_init_nand.c is the setup for
the L2 cache as SRAM. In the end is a loop that fills the
cache
At 14:17 03.02.2011 +0100, Fabian Cenedese wrote:
Hi
I'm creating a SPL u-boot image for our board. In the file
arch/powerpc/cpu/mpc85xx/cpu_init_nand.c is the setup for
the L2 cache as SRAM. In the end is a loop that fills the
cache with 0 (512KB in this case).
/* Initialize L2 SRAM to
Hi
I'm creating a SPL u-boot image for our board. In the file
arch/powerpc/cpu/mpc85xx/cpu_init_nand.c is the setup for
the L2 cache as SRAM. In the end is a loop that fills the
cache with 0 (512KB in this case).
/* Initialize L2 SRAM to zero */
l2srbar = (char
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