Hi Wouter,
On Friday 24 July 2009 09:48:17 Wouter Eckhardt wrote:
> Yes, I've checked the VxWorks kernel code. The comments mention that if
> caching is enabled, the cache should be flushed before the call to MMU
> TLB initialization is done. However, the calling code never actually
> flushes the
Hi Stefan,
Thanks for the quick reply.
> On Thursday 23 July 2009 20:39:44 Wouter Eckhardt wrote:
> > I'm working on trying to get VxWorks to boot on a PPC440GX processor
> > using U-Boot, using an ALPR board. In order to boot VxWorks properly
(it
> > expects caching on the SDRAM to be disabled),
Hi Wouter,
On Thursday 23 July 2009 20:39:44 Wouter Eckhardt wrote:
> I'm working on trying to get VxWorks to boot on a PPC440GX processor
> using U-Boot, using an ALPR board. In order to boot VxWorks properly (it
> expects caching on the SDRAM to be disabled), I created a new board
> directory an
Hi all,
I'm working on trying to get VxWorks to boot on a PPC440GX processor
using U-Boot, using an ALPR board. In order to boot VxWorks properly (it
expects caching on the SDRAM to be disabled), I created a new board
directory and such (based on the ALPR board), and then changed the TLB
settings
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