On 05/26/2016 01:39 PM, Alexey Brodkin wrote:
> Hi Marek,
Hi!
> On Fri, 2016-04-15 at 15:49 +0200, Marek Vasut wrote:
>> On 04/15/2016 03:00 PM, Alexey Brodkin wrote:
>>> Cache management functions should be implemented per arch or platform and so
>>> that they match requirements of underlying
On Thursday 26 May 2016 05:09 PM, Alexey Brodkin wrote:
> In the code you were referring what I wanted to modify reset vector of the
> slave core.
> And while we were living without IOC it was all OK. My code above wrote-back
> (or as we used to call it within ARC "flushed") L1 data cache with
Hi Marek,
On Fri, 2016-04-15 at 15:49 +0200, Marek Vasut wrote:
> On 04/15/2016 03:00 PM, Alexey Brodkin wrote:
> > Cache management functions should be implemented per arch or platform and so
> > that they match requirements of underlying hardware. If hardware may only
> > work on
> > whole
On 04/15/2016 03:00 PM, Alexey Brodkin wrote:
> Hi Marek,
>
> On Mon, 2016-04-11 at 20:48 +0200, Marek Vasut wrote:
>> On 04/11/2016 08:13 PM, Alexey Brodkin wrote:
>>>
>>> Hi Marek,
>>>
>>> On Mon, 2016-04-11 at 19:54 +0200, Marek Vasut wrote:
On 04/11/2016 07:48 PM, Alexey Brodkin
Hi Marek,
On Mon, 2016-04-11 at 20:48 +0200, Marek Vasut wrote:
> On 04/11/2016 08:13 PM, Alexey Brodkin wrote:
> >
> > Hi Marek,
> >
> > On Mon, 2016-04-11 at 19:54 +0200, Marek Vasut wrote:
> > >
> > > On 04/11/2016 07:48 PM, Alexey Brodkin wrote:
> > > >
> > > >
> > > > Hi Alex,
> > > >
On 04/11/2016 08:13 PM, Alexey Brodkin wrote:
> Hi Marek,
>
> On Mon, 2016-04-11 at 19:54 +0200, Marek Vasut wrote:
>> On 04/11/2016 07:48 PM, Alexey Brodkin wrote:
>>>
>>> Hi Alex,
>>>
>>> On Mon, 2016-04-04 at 09:38 +0200, Alexander Graf wrote:
Hi Alexey,
Marek just pointed
Hi Marek,
On Mon, 2016-04-11 at 19:54 +0200, Marek Vasut wrote:
> On 04/11/2016 07:48 PM, Alexey Brodkin wrote:
> >
> > Hi Alex,
> >
> > On Mon, 2016-04-04 at 09:38 +0200, Alexander Graf wrote:
> > >
> > > Hi Alexey,
> > >
> > > Marek just pointed out to me the fact that flush_dcache_range on
On 04/11/2016 07:48 PM, Alexey Brodkin wrote:
> Hi Alex,
>
> On Mon, 2016-04-04 at 09:38 +0200, Alexander Graf wrote:
>> Hi Alexey,
>>
>> Marek just pointed out to me the fact that flush_dcache_range on arm
>> expects cache line aligned arguments. However, it seems like in axs101.c
>> we have an
Hi Alex,
On Mon, 2016-04-04 at 09:38 +0200, Alexander Graf wrote:
> Hi Alexey,
>
> Marek just pointed out to me the fact that flush_dcache_range on arm
> expects cache line aligned arguments. However, it seems like in axs101.c
> we have an unaligned cache flush:
>
>
Hi Alexey,
Marek just pointed out to me the fact that flush_dcache_range on arm
expects cache line aligned arguments. However, it seems like in axs101.c
we have an unaligned cache flush:
flush_dcache_range(RESET_VECTOR_ADDR, RESET_VECTOR_ADDR + sizeof(int));
Could you please verify whether
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