> -Original Message-
> From: Joakim Tjernlund [mailto:joakim.tjernl...@infinera.com]
> Sent: Thursday, September 07, 2017 2:55 PM
> To: Mingkai Hu ; Roy Zang ;
> York Sun
> Cc: u-boot@lists.denx.de
> Subject: Re: setup of
On Thu, 2017-09-07 at 06:45 +, Mingkai Hu wrote:
> > -Original Message-
> > From: Mingkai Hu
> > Sent: Wednesday, September 06, 2017 5:37 PM
> > To: 'Joakim Tjernlund' ; Roy Zang
> > ; York Sun
> > Cc:
> -Original Message-
> From: Mingkai Hu
> Sent: Wednesday, September 06, 2017 5:37 PM
> To: 'Joakim Tjernlund' ; Roy Zang
> ; York Sun
> Cc: u-boot@lists.denx.de
> Subject: RE: setup of PEX_GCLK_RATIO in E500 CPUs(P2010)
On Wed, 2017-09-06 at 09:36 +, Mingkai Hu wrote:
> > -Original Message-
> > From: Joakim Tjernlund [mailto:joakim.tjernl...@infinera.com]
> > Sent: Tuesday, September 05, 2017 8:45 PM
> > To: Mingkai Hu ; Roy Zang ;
> > York Sun
> -Original Message-
> From: Joakim Tjernlund [mailto:joakim.tjernl...@infinera.com]
> Sent: Tuesday, September 05, 2017 8:45 PM
> To: Mingkai Hu ; Roy Zang ;
> York Sun
> Cc: u-boot@lists.denx.de
> Subject: Re: setup of
On Wed, 2017-08-30 at 15:25 +, York Sun wrote:
> On 08/30/2017 06:05 AM, Joakim Tjernlund wrote:
> > On Tue, 2017-08-29 at 17:33 +, York Sun wrote:
> > > +Roy Zang to comment on PCIe clock source
> > >
> > > On 08/29/2017 10:06 AM, Joakim Tjernlund wrote:
> > > > On Tue, 2017-08-29 at
On Wed, 2017-08-30 at 15:25 +, York Sun wrote:
> On 08/30/2017 06:05 AM, Joakim Tjernlund wrote:
> > On Tue, 2017-08-29 at 17:33 +, York Sun wrote:
> > > +Roy Zang to comment on PCIe clock source
> > >
> > > On 08/29/2017 10:06 AM, Joakim Tjernlund wrote:
> > > > On Tue, 2017-08-29 at
On 08/30/2017 06:05 AM, Joakim Tjernlund wrote:
> On Tue, 2017-08-29 at 17:33 +, York Sun wrote:
>> +Roy Zang to comment on PCIe clock source
>>
>> On 08/29/2017 10:06 AM, Joakim Tjernlund wrote:
>>> On Tue, 2017-08-29 at 15:43 +, York Sun wrote:
On 08/29/2017 06:21 AM, Joakim
On Tue, 2017-08-29 at 17:33 +, York Sun wrote:
> +Roy Zang to comment on PCIe clock source
>
> On 08/29/2017 10:06 AM, Joakim Tjernlund wrote:
> > On Tue, 2017-08-29 at 15:43 +, York Sun wrote:
> > > On 08/29/2017 06:21 AM, Joakim Tjernlund wrote:
> > > > On Tue, 2017-08-29 at 12:47
+Roy Zang to comment on PCIe clock source
On 08/29/2017 10:06 AM, Joakim Tjernlund wrote:
> On Tue, 2017-08-29 at 15:43 +, York Sun wrote:
>> On 08/29/2017 06:21 AM, Joakim Tjernlund wrote:
>>> On Tue, 2017-08-29 at 12:47 +0200, Joakim Tjernlund wrote:
As we are looking at PCI stuff ATM
On Tue, 2017-08-29 at 15:43 +, York Sun wrote:
> On 08/29/2017 06:21 AM, Joakim Tjernlund wrote:
> > On Tue, 2017-08-29 at 12:47 +0200, Joakim Tjernlund wrote:
> > > As we are looking at PCI stuff ATM I would like to ask
> > > about PEX_GCLK_RATIO in E500 CPUs. I cannot find this is setup
> >
On 08/29/2017 06:21 AM, Joakim Tjernlund wrote:
> On Tue, 2017-08-29 at 12:47 +0200, Joakim Tjernlund wrote:
>> As we are looking at PCI stuff ATM I would like to ask
>> about PEX_GCLK_RATIO in E500 CPUs. I cannot find this is setup
>> at all for E500 but I THINK this is required.
>>
>> In 83xx
On 08/29/2017 03:47 AM, Joakim Tjernlund wrote:
> As we are looking at PCI stuff ATM I would like to ask
> about PEX_GCLK_RATIO in E500 CPUs. I cannot find this is setup
> at all for E500 but I THINK this is required.
>
> In 83xx one do:
> get_clocks();
> /* Configure the PCIE controller core
On Tue, 2017-08-29 at 12:47 +0200, Joakim Tjernlund wrote:
> As we are looking at PCI stuff ATM I would like to ask
> about PEX_GCLK_RATIO in E500 CPUs. I cannot find this is setup
> at all for E500 but I THINK this is required.
>
> In 83xx one do:
> get_clocks();
> /* Configure the PCIE
As we are looking at PCI stuff ATM I would like to ask
about PEX_GCLK_RATIO in E500 CPUs. I cannot find this is setup
at all for E500 but I THINK this is required.
In 83xx one do:
get_clocks();
/* Configure the PCIE controller core clock ratio */
out_le32(hose_cfg_base + PEX_GCLK_RATIO,
(((bus ?
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