On 10/29/20 5:06 PM, Etienne Carriere wrote:
> On Thu, 29 Oct 2020 at 12:26, Ard Biesheuvel wrote:
>> The point I made before was that secure and non-secure are two
>> disjoint address spaces. The fact that TZ firewalls exist where you
>> can move things from one side to the other does not impl
On Thu, 29 Oct 2020 at 17:35, Jerome Forissier wrote:
>
>
>
> On 10/29/20 5:06 PM, Etienne Carriere wrote:
> > On Thu, 29 Oct 2020 at 12:26, Ard Biesheuvel wrote:
> >> The point I made before was that secure and non-secure are two
> >> disjoint address spaces. The fact that TZ firewalls exist whe
On Thu, 29 Oct 2020 at 17:06, Etienne Carriere
wrote:
>
> On Thu, 29 Oct 2020 at 12:26, Ard Biesheuvel wrote:
> >
> > On Thu, 29 Oct 2020 at 11:40, Etienne Carriere
> > wrote:
> > >
> > > Dear all,
> > >
> > > CC some fellow OP-TEE guys for this secure memory description topic.
> > >
> > >
> > >
On Thu, 29 Oct 2020 at 12:26, Ard Biesheuvel wrote:
>
> On Thu, 29 Oct 2020 at 11:40, Etienne Carriere
> wrote:
> >
> > Dear all,
> >
> > CC some fellow OP-TEE guys for this secure memory description topic.
> >
> >
> > On Wed, 28 Oct 2020 at 11:33, Patrick DELAUNAY
> > wrote:
> > >
> > > Hi,
>
On Thu, 29 Oct 2020 at 11:40, Etienne Carriere
wrote:
>
> Dear all,
>
> CC some fellow OP-TEE guys for this secure memory description topic.
>
>
> On Wed, 28 Oct 2020 at 11:33, Patrick DELAUNAY
> wrote:
> >
> > Hi,
> >
> > > From: Ard Biesheuvel
> > > Sent: mardi 27 octobre 2020 22:05
> > >
> >
Dear all,
CC some fellow OP-TEE guys for this secure memory description topic.
On Wed, 28 Oct 2020 at 11:33, Patrick DELAUNAY wrote:
>
> Hi,
>
> > From: Ard Biesheuvel
> > Sent: mardi 27 octobre 2020 22:05
> >
> > On Tue, 27 Oct 2020 at 18:25, Tom Rini wrote:
> > >
> > > On Fri, Oct 09, 2020
Hi,
> From: Ard Biesheuvel
> Sent: mardi 27 octobre 2020 22:05
>
> On Tue, 27 Oct 2020 at 18:25, Tom Rini wrote:
> >
> > On Fri, Oct 09, 2020 at 05:00:44PM +, Patrick DELAUNAY wrote:
> > > Hi Ard,
> > >
> > > > From: Ard Biesheuvel
> > > > Sent: mercredi 7 octobre 2020 15:16
> > > >
> > >
On Tue, 27 Oct 2020 at 18:25, Tom Rini wrote:
>
> On Fri, Oct 09, 2020 at 05:00:44PM +, Patrick DELAUNAY wrote:
> > Hi Ard,
> >
> > > From: Ard Biesheuvel
> > > Sent: mercredi 7 octobre 2020 15:16
> > >
> > > On Wed, 7 Oct 2020 at 13:53, Ahmad Fatoum wrote:
> > > >
> > > > Hello,
> > > >
> >
On Fri, Oct 09, 2020 at 05:00:44PM +, Patrick DELAUNAY wrote:
> Hi Ard,
>
> > From: Ard Biesheuvel
> > Sent: mercredi 7 octobre 2020 15:16
> >
> > On Wed, 7 Oct 2020 at 13:53, Ahmad Fatoum wrote:
> > >
> > > Hello,
> > >
> > > On 10/7/20 1:23 PM, Ahmad Fatoum wrote:
> > > > My findings[1] b
On Mon, 12 Oct 2020 at 11:51, Etienne Carriere
wrote:
>
> On Mon, 12 Oct 2020 at 11:20, Ard Biesheuvel wrote:
> >
> > On Mon, 12 Oct 2020 at 11:09, Etienne Carriere
> > wrote:
> > >
> > > On Fri, 9 Oct 2020 at 19:13, Ahmad Fatoum wrote:
> > > >
> > > > Hello Patrick,
> > > >
> > > > On 10/9/20
On Mon, 12 Oct 2020 at 11:20, Ard Biesheuvel wrote:
>
> On Mon, 12 Oct 2020 at 11:09, Etienne Carriere
> wrote:
> >
> > On Fri, 9 Oct 2020 at 19:13, Ahmad Fatoum wrote:
> > >
> > > Hello Patrick,
> > >
> > > On 10/9/20 5:52 PM, Patrick DELAUNAY wrote:
> > > > I checked DACR behavior and CheckDom
On Mon, 12 Oct 2020 at 11:09, Etienne Carriere
wrote:
>
> On Fri, 9 Oct 2020 at 19:13, Ahmad Fatoum wrote:
> >
> > Hello Patrick,
> >
> > On 10/9/20 5:52 PM, Patrick DELAUNAY wrote:
> > > I checked DACR behavior and CheckDomain / CheckPermission
> > >
> > > In my case the cortex A7 try to access
On Fri, 9 Oct 2020 at 19:13, Ahmad Fatoum wrote:
>
> Hello Patrick,
>
> On 10/9/20 5:52 PM, Patrick DELAUNAY wrote:
> > I checked DACR behavior and CheckDomain / CheckPermission
> >
> > In my case the cortex A7 try to access to part of DDR / mapped cacheable
> > and bufferable, protected by fire
On 10/9/20 7:12 PM, Ahmad Fatoum wrote:
> to do within normal world is mapping it XN, cacheable and not be in manager
> domain.
s/cacheable/uncacheable/ of course.
> Unmapping sounds unnecessary to me. (You don't unmap peripherals you aren't
> using either.
> Why handle OP-TEE DRAM specially?)
Hello Patrick,
On 10/9/20 5:52 PM, Patrick DELAUNAY wrote:
> I checked DACR behavior and CheckDomain / CheckPermission
>
> In my case the cortex A7 try to access to part of DDR / mapped cacheable and
> bufferable, protected by firewall.
>
> So to use DACR I always need to configure the MMU wit
On Fri, 9 Oct 2020 at 19:13, Ahmad Fatoum wrote:
>
> Hello Patrick,
>
> On 10/9/20 5:52 PM, Patrick DELAUNAY wrote:
> > I checked DACR behavior and CheckDomain / CheckPermission
> >
> > In my case the cortex A7 try to access to part of DDR / mapped cacheable
> > and bufferable, protected by fire
Hi Ard,
> From: Ard Biesheuvel
> Sent: mercredi 7 octobre 2020 15:16
>
> On Wed, 7 Oct 2020 at 13:53, Ahmad Fatoum wrote:
> >
> > Hello,
> >
> > On 10/7/20 1:23 PM, Ahmad Fatoum wrote:
> > > My findings[1] back then were that U-Boot did set the eXecute Never
> > > bit only on OMAP, but not for
Hi Ahmad,
> From: Ahmad Fatoum
> Sent: mercredi 7 octobre 2020 13:24
>
> Hello Ard, Patrick,
>
> On 10/7/20 12:26 PM, Ard Biesheuvel wrote:
> >> The issue is solved only when the region reserved by OP-TEE is no
> >> more mapped in U-Boot (mapped as DEVICE/NON-CACHEABLE wasn't
> enough)
> >> as
On Wed, 7 Oct 2020 at 17:08, Ard Biesheuvel wrote:
>
> On Wed, 7 Oct 2020 at 16:55, Etienne Carriere
> wrote:
> >
> > Hello all,
> >
> > On Wed, 7 Oct 2020 at 15:16, Ard Biesheuvel wrote:
> > >
> > > On Wed, 7 Oct 2020 at 13:53, Ahmad Fatoum wrote:
> > > >
> > > > Hello,
> > > >
> > > > On 10/7
On Wed, 7 Oct 2020 at 16:55, Etienne Carriere
wrote:
>
> Hello all,
>
> On Wed, 7 Oct 2020 at 15:16, Ard Biesheuvel wrote:
> >
> > On Wed, 7 Oct 2020 at 13:53, Ahmad Fatoum wrote:
> > >
> > > Hello,
> > >
> > > On 10/7/20 1:23 PM, Ahmad Fatoum wrote:
> > > > My findings[1] back then were that U-
Hello all,
On Wed, 7 Oct 2020 at 15:16, Ard Biesheuvel wrote:
>
> On Wed, 7 Oct 2020 at 13:53, Ahmad Fatoum wrote:
> >
> > Hello,
> >
> > On 10/7/20 1:23 PM, Ahmad Fatoum wrote:
> > > My findings[1] back then were that U-Boot did set the eXecute Never bit
> > > only on
> > > OMAP, but not for o
On Wed, 7 Oct 2020 at 13:53, Ahmad Fatoum wrote:
>
> Hello,
>
> On 10/7/20 1:23 PM, Ahmad Fatoum wrote:
> > My findings[1] back then were that U-Boot did set the eXecute Never bit
> > only on
> > OMAP, but not for other platforms. So I could imagine this being the root
> > cause
> > of Patrick'
Hello Ard, Patrick,
On 10/7/20 12:26 PM, Ard Biesheuvel wrote:
>> The issue is solved only when the region reserved by OP-TEE is no more
>> mapped in U-Boot (mapped as DEVICE/NON-CACHEABLE wasn't enough) as it is
>> already done in Linux kernel.
>>
>
> Spurious peculative accesses to device regio
Hello,
On 10/7/20 1:23 PM, Ahmad Fatoum wrote:
> My findings[1] back then were that U-Boot did set the eXecute Never bit only
> on
> OMAP, but not for other platforms. So I could imagine this being the root
> cause
> of Patrick's issues as well:
Rereading my own link, my memory is a little les
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