On 1/3/21 3:26 AM, Jernej Skrabec wrote: > H616 has mostly the same clocks as H6 with some small differences. Just > reuse H6 clocks for H616 and handle differences with macros. > > Signed-off-by: Jernej Skrabec <jernej.skra...@siol.net> > --- > .../include/asm/arch-sunxi/clock_sun50i_h6.h | 18 +++++++++++++++++- > arch/arm/mach-sunxi/clock_sun50i_h6.c | 10 +++++++++- > 2 files changed, 26 insertions(+), 2 deletions(-) > > diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h > b/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h > index e83e84ab6cab..62abfc4ef6bd 100644 > --- a/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h > +++ b/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h > @@ -230,6 +230,7 @@ struct sunxi_ccm_reg { > #define CCM_PLL1_CTRL_EN BIT(31) > #define CCM_PLL1_LOCK_EN BIT(29) > #define CCM_PLL1_LOCK BIT(28) > +#define CCM_PLL1_OUT_EN BIT(27) > #define CCM_PLL1_CLOCK_TIME_2 (2 << 24) > #define CCM_PLL1_CTRL_P(p) ((p) << 16) > #define CCM_PLL1_CTRL_N(n) ((n) << 8) > @@ -238,6 +239,7 @@ struct sunxi_ccm_reg { > #define CCM_PLL5_CTRL_EN BIT(31) > #define CCM_PLL5_LOCK_EN BIT(29) > #define CCM_PLL5_LOCK BIT(28) > +#define CCM_PLL5_OUT_EN BIT(27) > #define CCM_PLL5_CTRL_N(n) ((n) << 8) > #define CCM_PLL5_CTRL_DIV1(div1) ((div1) << 0) > #define CCM_PLL5_CTRL_DIV2(div0) ((div0) << 1) > @@ -252,7 +254,6 @@ struct sunxi_ccm_reg { > #define CCM_PLL6_CTRL_DIV1_MASK (0x1 << > CCM_PLL6_CTRL_DIV1_SHIFT) > #define CCM_PLL6_CTRL_DIV2_SHIFT 1 > #define CCM_PLL6_CTRL_DIV2_MASK (0x1 << > CCM_PLL6_CTRL_DIV2_SHIFT) > -#define CCM_PLL6_DEFAULT 0xa0006300 > > /* cpu_axi bit field*/ > #define CCM_CPU_AXI_MUX_MASK (0x3 << 24) > @@ -262,6 +263,9 @@ struct sunxi_ccm_reg { > #define CCM_CPU_AXI_AXI_MASK 0x3 > #define CCM_CPU_AXI_DEFAULT_FACTORS 0x301 > > +#ifdef CONFIG_MACH_SUN50I_H6 > +#define CCM_PLL6_DEFAULT 0xa0006300 > + > /* psi_ahb1_ahb2 bit field */ > #define CCM_PSI_AHB1_AHB2_DEFAULT 0x03000102 > > @@ -270,6 +274,18 @@ struct sunxi_ccm_reg { > > /* apb1 bit field */ > #define CCM_APB1_DEFAULT 0x03000102 > +#elif CONFIG_MACH_SUN50I_H616 > +#define CCM_PLL6_DEFAULT 0xa8003100 > + > +/* psi_ahb1_ahb2 bit field */ > +#define CCM_PSI_AHB1_AHB2_DEFAULT 0x03000002 > + > +/* ahb3 bit field */ > +#define CCM_AHB3_DEFAULT 0x03000002 > + > +/* apb1 bit field */ > +#define CCM_APB1_DEFAULT 0x03000102 > +#endif > > /* apb2 bit field */ > #define APB2_CLK_SRC_OSC24M (0x0 << 24) > diff --git a/arch/arm/mach-sunxi/clock_sun50i_h6.c > b/arch/arm/mach-sunxi/clock_sun50i_h6.c > index 6bd466915c11..a4cc1b53728b 100644 > --- a/arch/arm/mach-sunxi/clock_sun50i_h6.c > +++ b/arch/arm/mach-sunxi/clock_sun50i_h6.c > @@ -68,6 +68,9 @@ void clock_set_pll1(unsigned int clk) > > /* clk = 24*n/p, p is ignored if clock is >288MHz */ > writel(CCM_PLL1_CTRL_EN | CCM_PLL1_LOCK_EN | CCM_PLL1_CLOCK_TIME_2 | > +#ifdef CONFIG_MACH_SUN50I_H616 > + CCM_PLL1_OUT_EN | > +#endif > CCM_PLL1_CTRL_N(clk / 24000000), &ccm->pll1_cfg); > while (!(readl(&ccm->pll1_cfg) & CCM_PLL1_LOCK)) {} > > @@ -83,6 +86,11 @@ unsigned int clock_get_pll6(void) > { > struct sunxi_ccm_reg *const ccm = > (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; > +#ifdef CONFIG_MACH_SUN50I_H6 > + int m = 4; > +#else > + int m = 2; > +#endif
This looks like a good place for an IS_ENABLED ternary. > uint32_t rval = readl(&ccm->pll6_cfg); > int n = ((rval & CCM_PLL6_CTRL_N_MASK) >> CCM_PLL6_CTRL_N_SHIFT); > @@ -91,7 +99,7 @@ unsigned int clock_get_pll6(void) > int div2 = ((rval & CCM_PLL6_CTRL_DIV2_MASK) >> > CCM_PLL6_CTRL_DIV2_SHIFT) + 1; > /* The register defines PLL6-4X, not plain PLL6 */ Now it is PLL6-2X or PLL6-4X. With those adjustments: Reviewed-by: Samuel Holland <sam...@sholland.org> > - return 24000000 / 4 * n / div1 / div2; > + return 24000000 / m * n / div1 / div2; > } > > int clock_twi_onoff(int port, int state) >