Re: [u-boot PATCH] arm: mach-k3: am6_init: Prioritize MSMC traffic over DDR in NAVSS Northbridge

2021-09-08 Thread Nishanth Menon
On 12:24-20210908, Jan Kiszka wrote: [...] > Thanks a lot! > > Who will augment its description and push this again? I have a rebased > version [1] at least, slightly polished, but my commit log is possibly > not optimal yet. Done. https://patchwork.ozlabs.org/project/uboot/patch/20210908202859

Re: [u-boot PATCH] arm: mach-k3: am6_init: Prioritize MSMC traffic over DDR in NAVSS Northbridge

2021-09-08 Thread Jan Kiszka
On 08.09.21 06:22, Nishanth Menon wrote: > On 16:27-20210907, Tom Rini wrote: >> On Tue, Sep 07, 2021 at 09:41:23PM +0200, Jan Kiszka wrote: >>> On 02.09.21 08:36, Jan Kiszka wrote: On 28.07.21 11:10, Jan Kiszka wrote: > On 30.01.20 09:05, Roger Quadros wrote: > > [...] > >> #endif

Re: [u-boot PATCH] arm: mach-k3: am6_init: Prioritize MSMC traffic over DDR in NAVSS Northbridge

2021-09-07 Thread Nishanth Menon
On 16:27-20210907, Tom Rini wrote: > On Tue, Sep 07, 2021 at 09:41:23PM +0200, Jan Kiszka wrote: > > On 02.09.21 08:36, Jan Kiszka wrote: > > > On 28.07.21 11:10, Jan Kiszka wrote: > > >> On 30.01.20 09:05, Roger Quadros wrote: [...] > > >>> #endif /* __ASM_ARCH_AM6_HARDWARE_H */ > > >>> > > >>

Re: [u-boot PATCH] arm: mach-k3: am6_init: Prioritize MSMC traffic over DDR in NAVSS Northbridge

2021-09-07 Thread Tom Rini
On Tue, Sep 07, 2021 at 09:41:23PM +0200, Jan Kiszka wrote: > On 02.09.21 08:36, Jan Kiszka wrote: > > On 28.07.21 11:10, Jan Kiszka wrote: > >> On 30.01.20 09:05, Roger Quadros wrote: > >>> NB0 is bridge to SRAM and NB1 is bridge to DDR. > >>> > >>> To ensure that SRAM transfers are not stalled du

Re: [u-boot PATCH] arm: mach-k3: am6_init: Prioritize MSMC traffic over DDR in NAVSS Northbridge

2021-09-07 Thread Jan Kiszka
On 02.09.21 08:36, Jan Kiszka wrote: > On 28.07.21 11:10, Jan Kiszka wrote: >> On 30.01.20 09:05, Roger Quadros wrote: >>> NB0 is bridge to SRAM and NB1 is bridge to DDR. >>> >>> To ensure that SRAM transfers are not stalled due to >>> delays during DDR refreshes, SRAM traffic should be higher >>>

Re: [u-boot PATCH] arm: mach-k3: am6_init: Prioritize MSMC traffic over DDR in NAVSS Northbridge

2021-09-01 Thread Jan Kiszka
On 28.07.21 11:10, Jan Kiszka wrote: > On 30.01.20 09:05, Roger Quadros wrote: >> NB0 is bridge to SRAM and NB1 is bridge to DDR. >> >> To ensure that SRAM transfers are not stalled due to >> delays during DDR refreshes, SRAM traffic should be higher >> priority (threadmap=2) than DDR traffic (thre

Re: [u-boot PATCH] arm: mach-k3: am6_init: Prioritize MSMC traffic over DDR in NAVSS Northbridge

2021-07-28 Thread Jan Kiszka
On 30.01.20 09:05, Roger Quadros wrote: > NB0 is bridge to SRAM and NB1 is bridge to DDR. > > To ensure that SRAM transfers are not stalled due to > delays during DDR refreshes, SRAM traffic should be higher > priority (threadmap=2) than DDR traffic (threadmap=0). > > This patch does just that. >

[u-boot PATCH] arm: mach-k3: am6_init: Prioritize MSMC traffic over DDR in NAVSS Northbridge

2020-01-30 Thread Roger Quadros
NB0 is bridge to SRAM and NB1 is bridge to DDR. To ensure that SRAM transfers are not stalled due to delays during DDR refreshes, SRAM traffic should be higher priority (threadmap=2) than DDR traffic (threadmap=0). This patch does just that. This is required to fix ICSSG TX lock-ups due to delay