On 27. 02. 19 7:10, Chee, Tien Fong wrote:
> On Tue, 2019-02-26 at 16:43 +0100, Michal Simek wrote:
>> On 26. 02. 19 15:30, Chee, Tien Fong wrote:
>>>
>>> On Tue, 2019-02-26 at 15:07 +0100, Michal Simek wrote:
On 19. 02. 19 4:47, tien.fong.c...@intel.com wrote:
>
>
> From: Tie
On Tue, 2019-02-26 at 16:43 +0100, Michal Simek wrote:
> On 26. 02. 19 15:30, Chee, Tien Fong wrote:
> >
> > On Tue, 2019-02-26 at 15:07 +0100, Michal Simek wrote:
> > >
> > > On 19. 02. 19 4:47, tien.fong.c...@intel.com wrote:
> > > >
> > > >
> > > > From: Tien Fong Chee
> > > >
> > > > Add
On 26. 02. 19 15:30, Chee, Tien Fong wrote:
> On Tue, 2019-02-26 at 15:07 +0100, Michal Simek wrote:
>> On 19. 02. 19 4:47, tien.fong.c...@intel.com wrote:
>>>
>>> From: Tien Fong Chee
>>>
>>> Add default fitImage file bundling FPGA bitstreams for Arria10.
>>>
>>> Signed-off-by: Tien Fong Chee
>>
On Tue, 2019-02-26 at 15:07 +0100, Michal Simek wrote:
> On 19. 02. 19 4:47, tien.fong.c...@intel.com wrote:
> >
> > From: Tien Fong Chee
> >
> > Add default fitImage file bundling FPGA bitstreams for Arria10.
> >
> > Signed-off-by: Tien Fong Chee
> >
> > ---
> >
> > changes for v8
> > - Reo
On Tue, 2019-02-26 at 15:07 +0100, Michal Simek wrote:
> On 19. 02. 19 4:47, tien.fong.c...@intel.com wrote:
> >
> > From: Tien Fong Chee
> >
> > Add default fitImage file bundling FPGA bitstreams for Arria10.
> >
> > Signed-off-by: Tien Fong Chee
> >
> > ---
> >
> > changes for v8
> > - Reo
On 19. 02. 19 4:47, tien.fong.c...@intel.com wrote:
> From: Tien Fong Chee
>
> Add default fitImage file bundling FPGA bitstreams for Arria10.
>
> Signed-off-by: Tien Fong Chee
>
> ---
>
> changes for v8
> - Reordered the images and fpga configurations.
> - Removed the load property at core i
On 19. 02. 19 4:47, tien.fong.c...@intel.com wrote:
> From: Tien Fong Chee
>
> Add default fitImage file bundling FPGA bitstreams for Arria10.
>
> Signed-off-by: Tien Fong Chee
>
> ---
>
> changes for v8
> - Reordered the images and fpga configurations.
> - Removed the load property at core i
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