/151366.html
Andre Przywara (6):
ARM: add secure monitor handler to switch to non-secure state
ARM: add assembly routine to switch to non-secure state
ARM: add U-Boot command hypmode to switch to non-secure state
ARM: add SMP support for non-secure switch
ARM: extend non-secure switch
the MVBAR register
if the CPU supports the virtualization extensions.
Introduce a monitor handler routine which switches the CPU to
non-secure state by setting the NS bit (and associated bits).
Signed-off-by: Andre Przywara andre.przyw...@linaro.org
---
arch/arm/cpu/armv7/start.S | 20
registers r0-r3.
Signed-off-by: Andre Przywara andre.przyw...@linaro.org
---
arch/arm/cpu/armv7/start.S | 45 +
1 file changed, 45 insertions(+)
diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S
index 7bfb19d..401b0eb 100644
--- a/arch/arm
in the assembly routine.
The actual U-Boot command is pretty small: calling the routine and
doing some error reporting. A return value of 1 will be added later.
To enable the whole code we introduce the CONFIG_CMD_VIRT variable.
Signed-off-by: Andre Przywara andre.przyw...@linaro.org
---
arch/arm/include
for the Versatile Express board.
Signed-off-by: Andre Przywara andre.przyw...@linaro.org
---
arch/arm/cpu/armv7/start.S | 27 ++-
arch/arm/lib/virt-v7.c | 10 +-
include/configs/vexpress_ca15_tc2.h | 1 +
3 files changed, 36 insertions(+), 2 deletions
Enable the hypmode command for the Versatile Express TC2 board
with the virtualization capable Cortex-A15 CPU to allow booting
Xen or a KVM-enabled Linux kernel in HYP mode.
Signed-off-by: Andre Przywara andre.przyw...@linaro.org
---
include/configs/vexpress_ca15_tc2.h | 2 ++
1 file changed, 2
error reporting.
Signed-off-by: Andre Przywara andre.przyw...@linaro.org
---
arch/arm/cpu/armv7/start.S | 34 +++---
arch/arm/include/asm/armv7.h | 2 +-
arch/arm/lib/virt-v7.c | 24
common/cmd_virt.c| 20
On 04/26/2013 03:18 PM, Peter Maydell wrote:
On 26 April 2013 14:14, Andre Przywara andre.przyw...@linaro.org wrote:
ARM CPUs with the virtualization extension have a new mode called
HYP mode, which allows hypervisors to safely control and monitor
guests. The current hypervisor (KVM and Xen
On 04/26/2013 03:42 PM, Peter Maydell wrote:
On 26 April 2013 14:24, Andre Przywara andre.przyw...@linaro.org wrote:
On 04/26/2013 03:18 PM, Peter Maydell wrote:
The obvious question here is why do we need a new command?.
The kernel booting specification says boot the kernel in
Hyp mode so we
recommendation
* adding comment as proposed by Christoffer
Please review and comment!
Contributions and comments to support other boards are welcome.
Andre.
[1] http://lists.denx.de/pipermail/u-boot/2013-April/151366.html
Andre Przywara (6):
ARM: add secure monitor handler to switch to non-secure
on accessing MVBAR otherwise.
Signed-off-by: Andre Przywara andre.przyw...@linaro.org
---
arch/arm/cpu/armv7/start.S | 31 ---
1 file changed, 28 insertions(+), 3 deletions(-)
diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S
index e9e57e6..da48b36 100644
registers r0-r3.
Signed-off-by: Andre Przywara andre.przyw...@linaro.org
---
arch/arm/cpu/armv7/start.S | 47 ++
1 file changed, 47 insertions(+)
diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S
index da48b36..e63e892 100644
--- a/arch/arm
-off-by: Andre Przywara andre.przyw...@linaro.org
---
arch/arm/include/asm/armv7.h | 7 +++
arch/arm/lib/Makefile| 2 +
arch/arm/lib/bootm.c | 20
arch/arm/lib/virt-v7.c | 113 +++
4 files changed, 142 insertions(+)
create
for the Versatile Express board.
Signed-off-by: Andre Przywara andre.przyw...@linaro.org
---
arch/arm/cpu/armv7/start.S | 27 ++-
arch/arm/include/asm/armv7.h| 1 +
arch/arm/lib/virt-v7.c | 9 -
include/configs/vexpress_ca15_tc2.h | 1 +
4 files
Switch to HYP mode during bootm execution for the Versatile Express
TC2 board with the virtualization capable Cortex-A15 CPU to allow
booting Xen or a KVM-enabled Linux kernel in HYP mode.
Signed-off-by: Andre Przywara andre.przyw...@linaro.org
---
include/configs/vexpress_ca15_tc2.h | 2 ++
1
some error reporting.
Signed-off-by: Andre Przywara andre.przyw...@linaro.org
---
arch/arm/cpu/armv7/start.S | 34 +++---
arch/arm/include/asm/armv7.h | 4 ++--
arch/arm/lib/bootm.c | 12 +---
arch/arm/lib/virt-v7.c | 22
On 04/27/2013 12:13 AM, Christoffer Dall wrote:
On Fri, Apr 26, 2013 at 6:14 AM, Andre Przywara
andre.przyw...@linaro.org wrote:
Currently the non-secure switch is only done for the boot processor.
To later allow full SMP support, we have to switch all secondary
cores into non-secure state also
On 05/23/2013 12:52 PM, Albert ARIBAUD wrote:
Hi Andre,
On Mon, 6 May 2013 15:17:44 +0200, Andre Przywara
andre.przyw...@linaro.org wrote:
(for GIT URL and Changelog see below)
ARM CPUs with the virtualization extension have a new mode called
HYP mode, which allows hypervisors to safely
On 05/23/2013 12:52 PM, Albert ARIBAUD wrote:
Hi Andre,
On Mon, 6 May 2013 15:17:45 +0200, Andre Przywara
andre.przyw...@linaro.org wrote:
A prerequisite for using virtualization is to be in HYP mode, which
requires the CPU to be in non-secure state.
Introduce a monitor handler routine which
On 05/31/2013 08:11 AM, Christoffer Dall wrote:
On Mon, May 06, 2013 at 03:17:44PM +0200, Andre Przywara wrote:
(for GIT URL and Changelog see below)
ARM CPUs with the virtualization extension have a new mode called
HYP mode, which allows hypervisors to safely control and monitor
guests
On 05/31/2013 03:02 AM, Christoffer Dall wrote:
Christoffer,
thanks a lot for the thorough review. Comments inline.
On Mon, May 06, 2013 at 03:17:45PM +0200, Andre Przywara wrote:
A prerequisite for using virtualization is to be in HYP mode, which
requires the CPU to be in non-secure state
On 05/31/2013 05:04 AM, Christoffer Dall wrote:
On Mon, May 06, 2013 at 03:17:46PM +0200, Andre Przywara wrote:
While actually switching to non-secure state is one thing, the
more important part of this process is to make sure that we still
have full access to the interrupt controller (GIC
On 05/31/2013 07:10 AM, Christoffer Dall wrote:
On Mon, May 06, 2013 at 03:17:47PM +0200, Andre Przywara wrote:
To actually trigger the non-secure switch we just implemented, call
the switching routine from within the bootm command implementation.
This way we automatically enable this feature
On 05/31/2013 07:32 AM, Christoffer Dall wrote:
On Mon, May 06, 2013 at 03:17:48PM +0200, Andre Przywara wrote:
Currently the non-secure switch is only done for the boot processor.
To later allow full SMP support, we have to switch all secondary
cores into non-secure state also.
So we add
On 05/31/2013 07:43 AM, Christoffer Dall wrote:
On Mon, May 06, 2013 at 03:17:49PM +0200, Andre Przywara wrote:
For the KVM and XEN hypervisors to be usable, we need to enter the
kernel in HYP mode. Now that we already are in non-secure state,
HYP mode switching is within short reach.
While
review and comment!
I am pretty sure I missed some of the comments from the earlier
series, so if you find something that was mentioned before, feel
free to repeat it.
Contributions and comments to support other boards are welcome.
Andre Przywara (7):
ARM: prepare armv7.h to be included from
armv7.h contains some useful constants, but also C prototypes.
To include it also in assembly files, protect the non-assembly
part appropriately.
Signed-off-by: Andre Przywara andre.przyw...@linaro.org
---
arch/arm/include/asm/armv7.h | 6 +-
1 file changed, 5 insertions(+), 1 deletion
architecture reference manual this should not be
done in SVC mode, so we have to setup a SMC handler for this.
We create a new vector table to avoid interference with other boards.
The MVBAR register will be programmed later just before the smc call.
Signed-off-by: Andre Przywara andre.przyw...@linaro.org
Express board.
Signed-off-by: Andre Przywara andre.przyw...@linaro.org
---
arch/arm/cpu/armv7/nonsec_virt.S| 27 +++
arch/arm/include/asm/armv7.h| 1 +
arch/arm/lib/virt-v7.c | 19 ++-
include/configs/vexpress_ca15_tc2.h | 3 +++
4
-by: Andre Przywara andre.przyw...@linaro.org
---
arch/arm/cpu/armv7/nonsec_virt.S | 31 ---
arch/arm/include/asm/armv7.h | 7 +--
arch/arm/lib/bootm.c | 14 ++
arch/arm/lib/virt-v7.c | 27 ++-
4 files changed
To enable hypervisors utilizing the ARMv7 virtualization extension
on the Versatile Express board with the A15 core tile, we add the
respective configuration variable.
Signed-off-by: Andre Przywara andre.przyw...@linaro.org
---
include/configs/vexpress_ca15_tc2.h | 2 ++
1 file changed, 2
to call this routine also directly from the smp_pen
later (where we don't have any stack), we can only use caller saved
registers r0-r3 and r12 to not disturb the compiler.
Signed-off-by: Andre Przywara andre.przyw...@linaro.org
---
arch/arm/cpu/armv7/nonsec_virt.S | 66
.
The actual bootm trigger is pretty small: calling the routine and
doing some error reporting.
Signed-off-by: Andre Przywara andre.przyw...@linaro.org
---
arch/arm/include/asm/armv7.h| 7 ++
arch/arm/lib/Makefile | 2 +
arch/arm/lib/bootm.c| 20
On 06/21/2013 04:38 PM, Nikolay Nikolaev wrote:
Hello,
On Thu, Jun 13, 2013 at 2:01 PM, Andre Przywara
andre.przyw...@linaro.org mailto:andre.przyw...@linaro.org wrote:
For the KVM and XEN hypervisors to be usable, we need to enter the
kernel in HYP mode. Now that we already
On 06/28/2013 03:00 AM, Masahiro Yamada wrote:
Hello Andre,
Hi,
thanks a lot for the review! I included most of the fixes you proposed
in the next version I will send out soon.
Very useful comments, thanks again!
diff --git a/arch/arm/include/asm/armv7.h b/arch/arm/include/asm/armv7.h
index
On 06/28/2013 05:18 AM, Masahiro Yamada wrote:
Hi Andre.
--- a/arch/arm/lib/Makefile
+++ b/arch/arm/lib/Makefile
@@ -60,6 +60,8 @@ COBJS-y += reset.o
COBJS-y += cache.o
COBJS-y += cache-cp15.o
+COBJS-$(CONFIG_ARMV7_VIRT) += virt-v7.o
+
Judging from the file name
On 06/28/2013 05:51 AM, Masahiro Yamada wrote:
Hi Andre
[RFC]
I'd like to suggest to separate HYP-switching code
from Non-secure switching.
Thanks for stepping up and providing a use-case!
The first version of the patches had those two separate cases, but I
later merged them in favor of
-by: Andre Przywara andre.przyw...@linaro.org
---
arch/arm/cpu/armv7/Makefile | 2 +-
arch/arm/cpu/armv7/nonsec_virt.S | 43 +++-
arch/arm/cpu/armv7/virt-v7.c | 31 +
arch/arm/include/asm/armv7.h | 9 +++--
arch/arm/lib
architecture reference manual this should not be
done in SVC mode, so we have to setup a SMC handler for this.
We create a new vector table to avoid interference with other boards.
The MVBAR register will be programmed later just before the smc call.
Signed-off-by: Andre Przywara andre.przyw...@linaro.org
Express board.
Signed-off-by: Andre Przywara andre.przyw...@linaro.org
---
arch/arm/cpu/armv7/nonsec_virt.S| 27 +++
arch/arm/cpu/armv7/virt-v7.c| 19 ++-
arch/arm/include/asm/armv7.h| 1 +
arch/arm/include/asm/gic.h | 2
and
doing some error reporting.
Signed-off-by: Andre Przywara andre.przyw...@linaro.org
---
arch/arm/cpu/armv7/Makefile | 1 +
arch/arm/cpu/armv7/virt-v7.c | 117 +++
arch/arm/include/asm/armv7.h | 10
arch/arm/lib/bootm.c | 28 +++
4 files
armv7.h contains some useful constants, but also C prototypes.
To include it also in assembly files, protect the non-assembly
part appropriately.
Signed-off-by: Andre Przywara andre.przyw...@linaro.org
---
arch/arm/include/asm/armv7.h | 6 +-
1 file changed, 5 insertions(+), 1 deletion
-secure GIC CPU interface, since this register is banked.
Since we need to call this routine also directly from the smp_pen
later (where we don't have any stack), we can only use caller saved
registers r0-r3 and r12 to not mess with the compiler.
Signed-off-by: Andre Przywara andre.przyw...@linaro.org
that was mentioned before, feel
free to repeat it.
Contributions and comments to support other boards are welcome.
Andre Przywara (7):
ARM: prepare armv7.h to be included from assembly source
ARM: add secure monitor handler to switch to non-secure state
ARM: add assembly routine to switch to non
To enable hypervisors utilizing the ARMv7 virtualization extension
on the Versatile Express board with the A15 core tile, we add the
respective configuration variable.
Signed-off-by: Andre Przywara andre.przyw...@linaro.org
---
include/configs/vexpress_ca15_tc2.h | 2 ++
1 file changed, 2
On 07/30/2013 12:02 AM, Christoffer Dall wrote:
On Wed, Jul 10, 2013 at 01:54:16AM +0200, Andre Przywara wrote:
[...]
diff --git a/arch/arm/lib/bootm.c b/arch/arm/lib/bootm.c
index 1b6e0ac..7b0619e 100644
--- a/arch/arm/lib/bootm.c
+++ b/arch/arm/lib/bootm.c
@@ -34,6 +34,10 @@
#include asm
On 07/30/2013 12:02 AM, Christoffer Dall wrote:
n Wed, Jul 10, 2013 at 01:54:14AM +0200, Andre Przywara wrote:
A prerequisite for using virtualization is to be in HYP mode, which
requires the CPU to be in non-secure state first.
Add new file in arch/arm/cpu/armv7 to hold a monitor handler
On 07/30/2013 12:02 AM, Christoffer Dall wrote:
On Wed, Jul 10, 2013 at 01:54:17AM +0200, Andre Przywara wrote:
Currently the non-secure switch is only done for the boot processor.
To enable full SMP support, we have to switch all secondary cores
into non-secure state also.
So we add an entry
On 07/30/2013 12:02 AM, Christoffer Dall wrote:
On Wed, Jul 10, 2013 at 01:54:18AM +0200, Andre Przywara wrote:
For the KVM and XEN hypervisors to be usable, we need to enter the
kernel in HYP mode. Now that we already are in non-secure state,
HYP mode switching is within short reach.
While
in the assembly routine.
Signed-off-by: Andre Przywara andre.przyw...@linaro.org
---
arch/arm/cpu/armv7/Makefile | 1 +
arch/arm/cpu/armv7/virt-v7.c | 121 +++
arch/arm/include/asm/armv7.h | 3 ++
3 files changed, 125 insertions(+)
create mode 100644 arch/arm/cpu
To actually trigger the non-secure switch we just implemented, call
the switching routine from within the bootm command implementation.
This way we automatically enable this feature without further user
intervention.
Signed-off-by: Andre Przywara andre.przyw...@linaro.org
---
arch/arm/lib
-secure GIC CPU interface, since this register is banked.
Since we need to call this routine also directly from the smp_pen
later (where we don't have any stack), we can only use caller saved
registers r0-r3 and r12 to not mess with the compiler.
Signed-off-by: Andre Przywara andre.przyw...@linaro.org
someone needs to tweak this for
a specific board.
The way of setting the secondary's start address is board specific,
so each supported board should implement smp_set_boot_cpu_addr().
Signed-off-by: Andre Przywara andre.przyw...@linaro.org
---
arch/arm/cpu/armv7/nonsec_virt.S | 22
architecture reference manual this should not be
done in SVC mode, so we have to setup a SMC handler for this.
We create a new vector table to avoid interference with other boards.
The MVBAR register will be programmed later just before the smc call.
Signed-off-by: Andre Przywara andre.przyw
armv7.h contains some useful constants, but also C prototypes.
To include it also in assembly files, protect the non-assembly
part appropriately.
Signed-off-by: Andre Przywara andre.przyw...@linaro.org
---
arch/arm/include/asm/armv7.h | 6 +-
1 file changed, 5 insertions(+), 1 deletion
to support other boards are welcome.
Andre Przywara (8):
ARM: prepare armv7.h to be included from assembly source
ARM: add secure monitor handler to switch to non-secure state
ARM: add assembly routine to switch to non-secure state
ARM: add C function to switch to non-secure state
ARM: trigger
cores
and smp_waitloop() to wait for IPIs and jump to the start address.
This also serves as an example for what to do when adding support for
new boards.
Signed-off-by: Andre Przywara andre.przyw...@linaro.org
---
board/armltd/vexpress/Makefile | 7 +--
board/armltd/vexpress
-by: Andre Przywara andre.przyw...@linaro.org
---
arch/arm/cpu/armv7/Makefile | 2 +-
arch/arm/cpu/armv7/nonsec_virt.S | 43 +++-
arch/arm/cpu/armv7/virt-v7.c | 37 ++
arch/arm/include/asm/armv7.h | 6 --
arch/arm/lib
On 08/09/2013 06:55 PM, Christoffer Dall wrote:
On Fri, Aug 09, 2013 at 05:03:04PM +0200, Andre Przywara wrote:
(for GIT URL and Changelog see below)
ARM CPUs with the virtualization extension have a new mode called
HYP mode, which allows hypervisors to safely control and monitor
guests
On 08/27/2013 02:23 AM, Masahiro Yamada wrote:
Hello Andre,
+/* the vector table for secure state */
+_monitor_vectors:
+ .word 0 /* reset */
+ .word 0 /* undef */
+ adr pc, _secure_monitor
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+
;-)
Contributions and comments to support other boards are welcome.
Andre Przywara (8):
ARM: prepare armv7.h to be included from assembly source
ARM: add secure monitor handler to switch to non-secure state
ARM: add assembly routine to switch to non-secure state
ARM: add C function
architecture reference manual this should not be
done in SVC mode, so we have to setup a SMC handler for this.
We create a new vector table to avoid interference with other boards.
The MVBAR register will be programmed later just before the smc call.
Signed-off-by: Andre Przywara andre.przyw
To actually trigger the non-secure switch we just implemented, call
the switching routine from within the bootm command implementation.
This way we automatically enable this feature without further user
intervention.
Signed-off-by: Andre Przywara andre.przyw...@linaro.org
---
arch/arm/lib
in the assembly routine.
Signed-off-by: Andre Przywara andre.przyw...@linaro.org
---
arch/arm/cpu/armv7/Makefile | 1 +
arch/arm/cpu/armv7/virt-v7.c | 122 +++
arch/arm/include/asm/armv7.h | 3 ++
3 files changed, 126 insertions(+)
create mode 100644 arch/arm/cpu
-secure GIC CPU interface, since this register is banked.
Since we need to call this routine also directly from the smp_pen
later (where we don't have any stack), we can only use caller saved
registers r0-r3 and r12 to not mess with the compiler.
Signed-off-by: Andre Przywara andre.przyw...@linaro.org
specific
manner.
There is no need to provide a custom smp_waitloop() function here.
This also serves as an example for what to do when adding support for
new boards.
Signed-off-by: Andre Przywara andre.przyw...@linaro.org
---
board/armltd/vexpress/vexpress_common.c | 15 +++
include
armv7.h contains some useful constants, but also C prototypes.
To include it also in assembly files, protect the non-assembly
part appropriately.
Signed-off-by: Andre Przywara andre.przyw...@linaro.org
---
arch/arm/include/asm/armv7.h | 6 +-
1 file changed, 5 insertions(+), 1 deletion
.
Signed-off-by: Andre Przywara andre.przyw...@linaro.org
---
arch/arm/cpu/armv7/Makefile | 2 +-
arch/arm/cpu/armv7/nonsec_virt.S | 43 +++-
arch/arm/cpu/armv7/virt-v7.c | 37 ++
arch/arm/include/asm/armv7.h | 6
.
Signed-off-by: Andre Przywara andre.przyw...@linaro.org
---
arch/arm/cpu/armv7/nonsec_virt.S | 35 +++
arch/arm/cpu/armv7/virt-v7.c | 16 +++-
arch/arm/include/asm/armv7.h | 1 +
arch/arm/include/asm/gic.h | 2 ++
include/common.h
On 09/19/2013 09:57 PM, Mj Embd wrote:
two quick points
(a) xen already has a mode_switch code, so AFAIK xen might not use it
(as suggested by comment in another patch in this patch set)
Just a few days ago Ian sent out patches to remove this code from Xen.
That code was never meant to
On 09/19/2013 10:38 PM, Mj Embd wrote:
Hello Christoffer,
I agree with both of you points.
What I found different in 2 approaches is that in your approach
S-Monitor-NS-Hyp using svc and hvc
While the other approach is setting the M bits directly in cpsr
Xen uses the following
cpsid aif,
On 09/17/2013 12:28 AM, Alexander Tarasikov wrote:
Hello, u-boot developers!
I am attaching a patch to enable the HYP (hypervisor)
mode on the OMAP5 CPU. It is based on a previous patch by
Ian Molton. For some reason, Ian's patch was incorrect
(loading PC with the wrong address, missing memory
Commit be3b51aa4a450f3e3fcd9c6e5074ef435812a02d renamed CONFIG_PMIC
to CONFIG_POWER, but somehow the old values survived or sneaked in
again.
Removed the redundant and useless version in exynos5250-dt.h and
rename it in arndale.h.
Signed-off-by: Andre Przywara andre.przyw...@linaro.org
for the SMDK5250 without the CROS_EC
define, so pull it in for this board too for the time being.
Signed-off-by: Andre Przywara andre.przyw...@linaro.org
---
include/configs/exynos5250-dt.h | 22 +-
include/configs/smdk5250.h | 1 +
include/configs/snow.h | 1
The config file exynos5250-dt.h is used by two boards currently.
To allow the Arndale board to use it too in the future, move some
board specific defines out of that generic file.
Update the copyright, header comment and include protection define
on the way.
Signed-off-by: Andre Przywara
Now that we have moved most of the board specific defines out of
exynos5250-dt.h, we can replace arndale.h with an include of that
generic file.
Define the remaining, Arndale-specific options after that.
Signed-off-by: Andre Przywara andre.przyw...@linaro.org
---
include/configs/arndale.h | 242
Przywara andre.przyw...@linaro.org
Andre Przywara (5):
ARM: Exynos5250: rename obsoleted CONFIG_PMIC defines
ARM: Exynos5250: remove redundant defines in exynos5250-dt.h
ARM: Exynos5250: move feature defines out of generic config file
ARM: snow: move defines for Chromebook embedded controller
For some reasons the very same defines appear twice in
exynos5250-dt.h. Remove the second version.
Signed-off-by: Andre Przywara andre.przyw...@linaro.org
---
include/configs/exynos5250-dt.h | 21 -
1 file changed, 21 deletions(-)
diff --git a/include/configs/exynos5250-dt.h
mode is just fine.
Signed-off-by: Andre Przywara andre.przyw...@linaro.org
---
arch/arm/cpu/armv7/start.S | 10 +++---
1 file changed, 7 insertions(+), 3 deletions(-)
diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S
index 36a4c3c..95c8a95 100644
--- a/arch/arm/cpu/armv7
, just
resolved some trivial merge conflicts and checkpatch complaints.
Patch 4/5 adds support for the A15 core tile, this is actually the
same as the A5 for now, but will be extended later.
Patch 5/5 enables bootz and hush parser for all boards, just for
convenience.
Regards,
Andre.
--
Andre
From: Ryan Harkin ryan.har...@linaro.org
This patch creates a new config for the A9 quad core tile that includes the
generic config for the Versatile Express platform.
Signed-off-by: Ryan Harkin ryan.har...@linaro.org
Signed-off-by: Andre Przywara andre.przyw...@linaro.org
---
MAINTAINERS
for the
dual core A5 core tile.
Signed-off-by: Ryan Harkin ryan.har...@linaro.org
Signed-off-by: Andre Przywara andre.przyw...@linaro.org
---
MAINTAINERS | 2 +-
board/armltd/vexpress/Makefile | 2 +-
board/armltd/vexpress/ca9x4_ct_vxp.c| 257
This adds support for the Cortex-A15-TC2 core tile for the Versatile
Express board by ARM. This is mostly a copy of the A5 support file,
but will be extended later with A15 specific options.
Signed-off-by: Andre Przywara andre.przyw...@linaro.org
---
boards.cfg | 1
Signed-off-by: Andre Przywara andre.przyw...@linaro.org
---
include/configs/vexpress_common.h | 4
1 file changed, 4 insertions(+)
diff --git a/include/configs/vexpress_common.h
b/include/configs/vexpress_common.h
index cd268e3..65d0ce4 100644
--- a/include/configs/vexpress_common.h
+++ b
not support the legacy
memory map.
Signed-off-by: Ryan Harkin ryan.har...@linaro.org
Signed-off-by: Andre Przywara andre.przyw...@linaro.org
---
MAINTAINERS | 1 +
board/armltd/vexpress/vexpress_common.c | 29 --
boards.cfg | 1
On 04/04/2013 12:06 PM, Albert ARIBAUD wrote:
Hi Andre,
On Wed, 3 Apr 2013 15:44:32 +0200, Andre Przywara
andre.przyw...@linaro.org wrote:
From: Ryan Harkin ryan.har...@linaro.org
The current ca9x4_ct_vxp platform contains support for a Versatile Express
motherboard with a quad core A9 core
On 04/04/2013 12:09 PM, Albert ARIBAUD wrote:
Hi Andre,
On Wed, 3 Apr 2013 15:44:33 +0200, Andre Przywara
andre.przyw...@linaro.org wrote:
From: Ryan Harkin ryan.har...@linaro.org
This patch creates a new config for the A9 quad core tile that includes the
generic config for the Versatile
This adds support for the Cortex-A15-TC2 core tile for the Versatile
Express board by ARM. This is mostly a copy of the A5 support file,
but will be extended later with A15 specific options.
Signed-off-by: Andre Przywara andre.przyw...@linaro.org
---
boards.cfg | 1
patches.
Andre: merged the first two of Ryan's original patches and did some
checkpatch fixes.
Signed-off-by: Ryan Harkin ryan.har...@linaro.org
Signed-off-by: Andre Przywara andre.przyw...@linaro.org
---
MAINTAINERS| 2 +-
board/armltd/vexpress/Makefile
Signed-off-by: Andre Przywara andre.przyw...@linaro.org
---
include/configs/vexpress_common.h | 5 +
1 file changed, 5 insertions(+)
diff --git a/include/configs/vexpress_common.h
b/include/configs/vexpress_common.h
index cd268e3..f5125c0 100644
--- a/include/configs/vexpress_common.h
+++ b
not support the legacy
memory map.
Signed-off-by: Ryan Harkin ryan.har...@linaro.org
Signed-off-by: Andre Przywara andre.przyw...@linaro.org
---
MAINTAINERS | 1 +
board/armltd/vexpress/vexpress_common.c | 29 --
boards.cfg | 1
bootz and hush parser for all boards, just for
convenience.
Changes:
v2:
- merge patch 1/5 and 2/5 as per Albert's request
- add support for raw initrd for full bootz experience
Regards,
Andre.
--
Andre Przywara
Linaro Virtualization Team
___
U-Boot
patches.
Andre: merged the first two of Ryan's original patches and did some
checkpatch fixes.
Signed-off-by: Ryan Harkin ryan.har...@linaro.org
Signed-off-by: Andre Przywara andre.przyw...@linaro.org
---
MAINTAINERS| 2 +-
board/armltd/vexpress/Makefile
This adds support for the Cortex-A15-TC2 core tile for the Versatile
Express board by ARM. This is mostly a copy of the A5 support file,
but will be extended later with A15 specific options.
Signed-off-by: Andre Przywara andre.przyw...@linaro.org
---
boards.cfg | 1
Signed-off-by: Andre Przywara andre.przyw...@linaro.org
---
include/configs/vexpress_common.h | 4
1 file changed, 4 insertions(+)
diff --git a/include/configs/vexpress_common.h
b/include/configs/vexpress_common.h
index cd268e3..3c5683a 100644
--- a/include/configs/vexpress_common.h
+++ b
not support the legacy
memory map.
Signed-off-by: Ryan Harkin ryan.har...@linaro.org
Signed-off-by: Andre Przywara andre.przyw...@linaro.org
---
MAINTAINERS | 1 +
board/armltd/vexpress/vexpress_common.c | 29 --
boards.cfg | 1
bootz and hush parser for all boards, just for
convenience.
Changes:
v3:
- drop now unneeded default prompt definition in patch 4
v2:
- merge patch 1/5 and 2/5 as per Albert's request
- add support for raw initrd for full bootz experience
Regards,
Andre.
--
Andre Przywara
Linaro Virtualization
On 01/08/14 13:53, Christoffer Dall wrote:
On 1 August 2014 14:46, Andreas Färber afaer...@suse.de wrote:
Hi,
Am 01.08.2014 13:35, schrieb Christoffer Dall:
From: Andre Przywara andre.przyw...@linaro.org
To enable hypervisors utilizing the ARMv7 virtualization extension
on the Arndale
On 01/08/14 14:02, Christoffer Dall wrote:
On 1 August 2014 14:59, Andre Przywara andre.przyw...@arm.com wrote:
On 01/08/14 13:53, Christoffer Dall wrote:
On 1 August 2014 14:46, Andreas Färber afaer...@suse.de wrote:
Hi,
Am 01.08.2014 13:35, schrieb Christoffer Dall:
From: Andre
Commit v2013.10-189-gb3a7f22 breaks u-boot on the VExpress TC2, since
the hardcoded value for SP804 timer address is wrong on Versatile
Express boards using the extended memory map.
Replace this value with an existing macro make it work on both sets of
machines.
Signed-off-by: Andre Przywara
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