Re: [U-Boot] [PATCH 09/23] boston: Disable PCI bridge memory space alignment

2016-09-28 Thread Bin Meng
On Tue, Sep 27, 2016 at 2:29 AM, Paul Burton wrote: > On the MIPS Boston development board we have an Intel EG20T Platform > Controller Hub connected to a Xilinx AXI to PCIe root port which is only > assigned a 1MB memory region. The Intel EG20T contains a bridge device >

Re: [U-Boot] [PATCH 09/23] boston: Disable PCI bridge memory space alignment

2016-09-26 Thread Simon Glass
On 26 September 2016 at 12:29, Paul Burton wrote: > On the MIPS Boston development board we have an Intel EG20T Platform > Controller Hub connected to a Xilinx AXI to PCIe root port which is only > assigned a 1MB memory region. The Intel EG20T contains a bridge device >

[U-Boot] [PATCH 09/23] boston: Disable PCI bridge memory space alignment

2016-09-26 Thread Paul Burton
On the MIPS Boston development board we have an Intel EG20T Platform Controller Hub connected to a Xilinx AXI to PCIe root port which is only assigned a 1MB memory region. The Intel EG20T contains a bridge device beneath which all of its peripheral devices can be found, and that bridge device