Hi,friends,
I made two boards of MPC8360E with u-boot-1.3.0, the hardware on the board is
the
same and the version of u-boot is also the same. One of the board is OK for
erase
and cp.b command in u-boot,I can tftp the uImage,ramdisk,dtb,cfg.jffs2 to DDR,
then I used the cp.b command to write th
> -Original Message-
> From: [EMAIL PROTECTED] [mailto:[EMAIL PROTECTED]
> On Behalf Of Jean-Christophe PLAGNIOL-VILLARD
> Sent: den 17 maj 2008 14:43
> To: u-boot-users@lists.sourceforge.net
> Subject: [U-Boot-Users] [PATCH] 82550_eeprom: Fix error: lvalue required as
> increment operand
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <[EMAIL PROTECTED]>
---
examples/82559_eeprom.c | 11 ---
1 files changed, 8 insertions(+), 3 deletions(-)
diff --git a/examples/82559_eeprom.c b/examples/82559_eeprom.c
index 1a121d4..a56edd4 100644
--- a/examples/82559_eeprom.c
+++ b/exa
You've forget ds1722 and AMD Elan cpu which use SPI too
Best Regards,
J.
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h
Hi all.
I have PXA270 board with embedded by vendor bootleader - "U-Boot 1.3.0".
I define that environment:
---
$ printenv
baudrate=115200
bootdelay=3
bootargs=video=pxafb:mode:800x480-16,active,pixclock:37000,left:100,right:1,hsynclen:10,upper:20,lower:1,vsynclen:10,outputen:1,pixclockpol:0
root=
board/amcc/makalu/init.S:
board/amcc/makalu/memory.c:
include/configs/makalu.h:
Makalu now uses the data cache for its primordial stack and data
area and leverages the common, shared parameter-based SDRAM
initialization code.
include/ppc405.h:
Redefined SDRAM configuration size mnemonics
This patch adds a non-EEPROM-driven SDRAM initialization function
driven by compile-time CFG_SDRAM_* parameters usable by 405EX(r)-based
boards that have discrete SDRAM chips rather than DIMMs.
This patch continues laying the ground work for moving out-of-assembly
and unifying the SDRAM initializa
This patch continues laying the ground work for moving out-of-assembly
and unifying the SDRAM initialization code for PowerPC 405EX[r]-based
boards.
To do so, this deduces by one the number of nearly-identical DRAM ECC
initialization implementations for PowerPC 4xx processors utilizing a
DDR/DDR2