On Wed, May 28, 2008 at 10:24 AM, Shinose <[EMAIL PROTECTED]> wrote:
> Hi,
>
> I am working on Nios2 custom board with intel CFI j3 flash and my data bus
> is only 16 bit wide. The cfi driver I have modified with asm/io calls in
> order to by pass the cache. But now cp.w is working and not the cp.
Hi,
I am working on Nios2 custom board with intel CFI j3 flash and my data bus
is only 16 bit wide. The cfi driver I have modified with asm/io calls in
order to by pass the cache. But now cp.w is working and not the cp.b and
cp.l . What could be the possible reason as the saveenv (writebuf) is als
JP wrote:
[snip]
>> JP
> This turned out to be a hardware problem: the DQM 0/1 lines that select
> 8 bits of a 32 bit location were reversed.
Hi JP,
Thanks for letting the list know what the problem and resolution was.
It is very important to close the loop. Too many people never post the
f
[EMAIL PROTECTED] wrote:
> Hi All,
>
> We have installed new u-boot boot loader in a customized board , upon
> booting from flash we are observing that all which is displaying is
> in reverse order , we are not able find what is exact problem. we
> checked the endiness of the compiled code, It wa
On Tue, 27 May 2008 10:44:32 +0200
Andre Schwarz <[EMAIL PROTECTED]> wrote:
> Do you want me to re-send a complete set of patches for the M7-Board
> against the latest version ?
>
I'd appreciate it since I seem to have lost the board config file.
Kim
Detlev Zundel wrote:
> Hi Wolfgang and Hugo,
>
> while studying the mail footer of Hugo, I found a slightly
> problematic phrasing:
>
>> THIS MESSAGE AND ALL...
>
> So Hugo, please get rid of that message or I will advise Wolfgang to
> heed your footer...
I got rid of the message.
Is everythin
On 11:52 Tue 27 May , Tor Krill wrote:
> Add support for Silicon Images sil3114 sata chip using libata
>
> Signed-off-by: Tor Krill <[EMAIL PROTECTED]>
> ---
> drivers/block/Makefile |1 +
> drivers/block/sata_sil3114.c | 845
> ++
> drivers
On May 27, 2008, at 1:24 PM, Anton Vorontsov wrote:
> This patch adds support for NAND on MPC8610HPCD target. We're using
> BAT7
> and LAW4 entries for 4MB NAND mapping.
>
> MPC8610HPCD has four NAND chips in one package, bases as follows:
> - 0xe840
> - 0xe844
> - 0xe848
> - 0xe84c
In message <[EMAIL PROTECTED]> you wrote:
> Wolfgang Denk wrote:
> > Signed-off-by: Sergei Poselenov <[EMAIL PROTECTED]>
> > ---
> > board/socrates/socrates.c | 13 +++--
> > include/configs/socrates.h |3 ++-
> > 2 files changed, 13 insertions(+), 3 deletions(-)
>
> Better subject
This patch adds support for NAND on MPC8610HPCD target. We're using BAT7
and LAW4 entries for 4MB NAND mapping.
MPC8610HPCD has four NAND chips in one package, bases as follows:
- 0xe840
- 0xe844
- 0xe848
- 0xe84c
Also, this patch adds some localbus definitions to mpc86xx.h (strai
On Tuesday 27 May 2008, Wolfgang Denk wrote:
> Signed-off-by: Sergei Poselenov <[EMAIL PROTECTED]>
> ---
> board/socrates/socrates.c | 13 +++--
> include/configs/socrates.h |3 ++-
> 2 files changed, 13 insertions(+), 3 deletions(-)
>
> diff --git a/board/socrates/socrates.c b/boar
All other u-boot architectures have an include/asm/errno.h, so
this change adds it to the mips include/asm-mips headers also.
Stolen from Linux 2.6.25.
Signed-off-by: Jason McMullan <[EMAIL PROTECTED]>
---
include/asm-mips/errno.h | 143 ++
1 files ch
I am attempting to craft an auto-updater image consisting of three files in
a FIT multi-image:
* u-boot.bin (Binary 512 KiB u-boot image)
* boot.itb (FIT Multi-image)
- vmlinux.bin.gz (Compressed Binary Linux Kernel)
- devices.dtb (Binary FDT Blob)
* root.img (JFFS2 File
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