This bug was fixed in the package xserver-xorg-video-intel -
2:2.21.2-0ubuntu1
---
xserver-xorg-video-intel (2:2.21.2-0ubuntu1) raring; urgency=low
* Merge from unreleased debian git.
- new upstream release (LP: #1120108)
-- Timo AaltonenMon, 11 Feb 2013 16:09:46 +0200
**
** Branch linked: lp:ubuntu/raring-proposed/xserver-xorg-video-intel
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https://bugs.launchpad.net/bugs/1120108
Title:
[i915gm] GPU lockup IPEHR: 0x7d8e0001
To manage notifications abou
commit 42a6b25817985e22e7d462be87fbd97973d96a29
Author: Chris Wilson
Date: Sat Feb 9 15:30:58 2013 +
sna: Fix alignment of the base of partial buffers for pre-G33 chipsets
The older chipsets have much more restrictive alignment rules for the
base address of tiled but unfenc
The patch I am mulling is:
diff --git a/src/sna/sna_render.c b/src/sna/sna_render.c
index 697b802..69ac21c 100644
--- a/src/sna/sna_render.c
+++ b/src/sna/sna_render.c
@@ -899,6 +899,9 @@ sna_render_pixmap_partial(struct sna *sna,
DBG(("%s: tile size for tiling %d: %dx%d, size=%d\n
Looks like the unfenced alignment of the tiled-X buffer is incorrect:
0x00628180: 0x7d8e0001: 3DSTATE_BUFFER_INFO
0x00628184: 0x03402000:color, tiling = X, pitch=8192
0x00628188: 0x041a5000:address
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