On 03/09/2019 18:40, Ярослав Лещинский wrote:
rv is equal to -1 after the try of mounting. Qspiflash driver was
checked separately for the write, read, erase operations.
Can someone suggest what to do here?
A self-contained example would be nice including the application
configuration ( stuf
On 9/3/19 9:14 AM, Jiri Gaisler wrote:
>
> Hmm, maybe clock driver code has been changed during the years to read
> or write some register bits that are illegal on the 3-chip ERC32. This
> would cause a trap to error mode and most likely a watchdog reset. I
> quickly looked through the ERC32 clock
Hello,
Now I'm struggling with mounting of jffs2 using my qspiflash driver.
main.c
#include
#include
#include
#include
#include
#include
#include
#include
#include "config.h"
#include "user.h"
#include "spiflash.h"
#define SPIFLASH_BLOCK_SIZE (0x100)
#define SPIFLASH_SIZE (0x100)
On 03/09/2019 12:02, Ярослав Лещинский wrote:
Sebastian, sorry I didn't get your point. Should I put main.c as a first
object for a compilation and linkage?
This should work:
-Wl,--gc-sections o-optimize/main.o -ljffs2 -lz -mthumb-mcpu=cortex-m4
-mfpu=fpv4-sp-d16 -mfloat-abi=hard
--
Seb
On 03/09/2019 11:06, Ярослав Лещинский wrote:
-Wl,--gc-sections -ljffs2 -lz -mthumb -mcpu=cortex-m4
-mfpu=fpv4-sp-d16 -mfloat-abi=hard o-optimize/main.o
/home/midnight/rtems/toolchain/5/lib/gcc/arm-rtems5/7.4.1/../../../../arm-rtems5/bin/ld:
o-optimize/main.o:(.rodata.rtems_filesystem_table+0
Hello Sebastian,
I'm using rtems5.
My stm32l4.cfg
include $(RTEMS_ROOT)/make/custom/default.cfg
RTEMS_CPU = arm
CPU_CFLAGS = -mthumb -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=hard
CFLAGS_OPTIMIZE_V = -O2 -g
CFLAGS_OPTIMIZE_V += -ffunction-sections -fdata-sections
LDFLAGS = -Wl,--gc-secti
Hmm, maybe clock driver code has been changed during the years to read
or write some register bits that are illegal on the 3-chip ERC32. This
would cause a trap to error mode and most likely a watchdog reset. I
quickly looked through the ERC32 clock driver code but could not see
anything obvious. I
