Thank you for the quick response.
I have another question.. if I have a custom IP core generated with
System Generator (Simulink/MatLab), can I integrate it with RFNoC?
Alice
Il 14/11/17 00:34, Marcus D. Leech via USRP-users ha scritto:
On 11/13/2017 06:18 PM, Alice Lo Valvo via
On 11/13/2017 06:18 PM, Alice Lo Valvo via USRP-users wrote:
Hi,
I'm working with USRP X series. I'm wondering if I can design my
custom IP Core (or project) with Vivado and then integrate it with
RFNoC. If yes, how can I do it?
Thank you in advance,
Alice
Hi,
I'm working with USRP X series. I'm wondering if I can design my custom
IP Core (or project) with Vivado and then integrate it with RFNoC. If
yes, how can I do it?
Thank you in advance,
Alice
___
USRP-users mailing list
Hi Mark. Have you tried ISE on Windows machine? The Xilinx Linux cable
drivers from that era were quite unreliable.
Alternatively, there are also some old blog posts about Linux workarounds:
http://dreamrunner.org/blog/2012/09/12/install-xilinx-ise-on-the-ubuntu/
-Robin
On Mon, Nov 13, 2017
On 11/13/2017 08:55 AM, Mark Koenig wrote:
Just to follow up, all of the voltages on J105, J104, and J107 are correct.
Mark
I would focus on trying to get Impact working in your environment.
The Xilinx support forums may be a more fruitful avenue for that part of the
problem.
On
Just to follow up, all of the voltages on J105, J104, and J107 are correct.
Mark
On 11/9/17, 6:15 PM, "Mark Koenig" wrote:
Robin and Marcus,
Thank you for the suggestions. Marcus, I did try and follow your
suggestion, however, I cannot
Dear list,
Little update on transmitting bursts and simultaneous receiving with
USRP B210. When I connect anything that has some path between TX/RX SMA
port's body and inner female sleeve contact (like 3dB attenuator or even
my finger) the output signal starts to look ok. I don't know what is