Re: [USRP-users] x300_dac_ctrl: timeout waiting for DAC PLL to lock

2019-04-08 Thread Faller, Lisa-Marie via USRP-users
Hi Nate, yes, we get this error even with no DB attached. RMA? Thanks and best wishes, Lisa Ursprüngliche Nachricht Von: Nate Temple Datum: 08.04.19 21:59 (GMT+01:00) An: "Faller, Lisa-Marie" Cc: usrp-users@lists.ettus.com Betreff: Re: [USRP-users] x300_dac_ctrl: timeout waiti

Re: [USRP-users] Maximal number of RFNoC-blocks

2019-04-08 Thread Jonathon Pendlum via USRP-users
Hi Rob, Yes it is possible. All of these modifications require editing the core FPGA code and UHD. Removing the DmaFIFO is not too difficult. Althought it can be done, I would not suggest modifying the Eth or PCIe interfaces. Jonathon On Tue, Apr 9, 2019 at 6:35 AM Rob Kossler wrote: > Hi Jona

[USRP-users] E310/E312 AD9361 Fast Tuning

2019-04-08 Thread Samuel Prager via USRP-users
Hello, We are currently seeing frequency tuning times of >100 ms, even when re-tuning to within 100 MHz of the previous frequency (wherein calibrations routines should not be rerunning). We are looking at ways to speed this up, including use of fast lock profiles. If anyone could provide poin

Re: [USRP-users] Maximal number of RFNoC-blocks

2019-04-08 Thread Rob Kossler via USRP-users
Hi Jonathon, Is it possible to increase the 10 available to 13 by: - building an HG image that only needs one 10GigE - excluding the DmaFIFO (assuming underruns not an issue w/o this block) - building without PCIe support (is this even possible?) Rob On Thu, Apr 4, 2019 at 10:12 AM Jonathon Pend

Re: [USRP-users] Changing sample rate while running.

2019-04-08 Thread Nate Temple via USRP-users
Hi Chance, What version of UHD are you using? Could you please give the UHD branch UHD-3.10 a try with your application to see if it makes any difference? Regards, Nate Temple On Mon, Apr 8, 2019 at 8:56 AM Chance Tarver via USRP-users < usrp-users@lists.ettus.com> wrote: > Hi all, > > I am wo

Re: [USRP-users] rfnoc build for an e320

2019-04-08 Thread Marcus D. Leech via USRP-users
On 04/08/2019 03:33 PM, Jason Matusiak via USRP-users wrote: I should be getting an e320 in this week, so I started to get my environment setup. I started off like I do for the e310 and ran the cross-compile shell script. I then sourced the environment. I cloned uhd and checked out rfnoc-dev

Re: [USRP-users] rfnoc build for an e320

2019-04-08 Thread Nate Temple via USRP-users
Hi Jason, You can disable the QT widgets (not needed on the E320 itself) by adding the cmake flag -DENABLE_QT=OFF Regards, Nate Temple On Mon, Apr 8, 2019 at 1:00 PM Nate Temple wrote: > Hi Jason, > > It looks like you are missing the package: python-setuptools > > Note, you should not use

Re: [USRP-users] rfnoc build for an e320

2019-04-08 Thread Nate Temple via USRP-users
Hi Jason, It looks like you are missing the package: python-setuptools Note, you should not use rfnoc-devel, but instead use a newer version of UHD like v3.14.0.0, and then you can enable RFNoC by adding the cmake flag -DENABLE_RFNOC=ON Regards, Nate Temple On Mon, Apr 8, 2019 at 12:34 PM Jaso

Re: [USRP-users] rfnoc build for an e320

2019-04-08 Thread Jason Matusiak via USRP-users
So I think I goofed. Not sure why I was pointing it to the mpm directory for the CMakeLists. When I do the normal ../ it builds fine. Now I end up with the issue I used to have with the e310 many moons ago. The sysroots doesn't have qt in it. So when I run a cmake of gr-ettus, I get this er

Re: [USRP-users] x300_dac_ctrl: timeout waiting for DAC PLL to lock

2019-04-08 Thread Nate Temple via USRP-users
Hi Lisa, This error usually points to a failure on the MB which requires a RMA. If you remove your custom DB and run uhd_usrp_probe against just the MB do you still get this error? Regards, Nate Temple On Mon, Apr 8, 2019 at 9:13 AM Faller, Lisa-Marie via USRP-users < usrp-users@lists.ettus.co

[USRP-users] rfnoc build for an e320

2019-04-08 Thread Jason Matusiak via USRP-users
I should be getting an e320 in this week, so I started to get my environment setup. I started off like I do for the e310 and ran the cross-compile shell script. I then sourced the environment. I cloned uhd and checked out rfnoc-devel like I usually do. Within uhd, I created a folder called

Re: [USRP-users] Two RFNOC tx blocks timing and Bus

2019-04-08 Thread Xingjian Chen via USRP-users
Hi Leo, I get your idea. Thank you. references: http://ettus.80997.x6.nabble.com/USRP-users-vita-time-td9675.html https://conferences.sigcomm.org/sigcomm/2013/papers/srif/p45.pdf https://corvid.io/2017/04/22/stupid-rfnoc-tricks-loopback/ https://files.ettus.com/manual/page_rtp.html https://s

Re: [USRP-users] (no subject)

2019-04-08 Thread Nick Foster via USRP-users
OK, I looked further into it. UHD registers out-of-tree block controllers using the UHD_RFNOC_BLOCK_REGISTER macro, which under the hood creates a static function and a fixture which calls it before main(). Problem is, when linking your out-of-tree executable, the linker sees that the static fixtur

[USRP-users] x300_dac_ctrl: timeout waiting for DAC PLL to lock

2019-04-08 Thread Faller, Lisa-Marie via USRP-users
Hi all, we see the following error when executing uhd_usrp_probe: '...x300_dac_ctrl: timeout waiting for DAC PLL to lock...' We are working on an x310 (2015) and built a custom RX-Board to it. This used to work fine; Recently we have another revision of the custom board and were trying to set the

[USRP-users] Changing sample rate while running.

2019-04-08 Thread Chance Tarver via USRP-users
Hi all, I am working on a project where I need to change the sampling rate occasionally while running my application. At an event where I need to change the sampling rate, I am currently calling the following function: set_tx_rate(new_rate, channel) The master clock is always set to 30.72MHz and

Re: [USRP-users] RFNOC RX_Streamer example

2019-04-08 Thread Marcus D. Leech via USRP-users
On 04/08/2019 03:33 AM, Ran Lifshitz via USRP-users wrote: Hi, I'm using UHD 3.14 with RFNOC implementation. I would like to switch from tcp sink stream (currently working) to a UHD rx stream. I'm not seeing any python example, and the only API i'm seeing in python is related to multiUSRP. F

Re: [USRP-users] (no subject)

2019-04-08 Thread John Medrano via USRP-users
Hello, We have verified that library is being linked. When we run nm | grep We see the following: 00030310 W _ZNK3uhd7device314get_block_ctrlINS_5rfnoc19_block_ctrlEEEN5boost10shared_ptrIT_EERKNS2_10block_id_tE 0023d6e0 V _ZTIN3uhd5rfnoc19_block_ctrlE 00034b00 V _ZTSN3

Re: [USRP-users] Two RFNOC tx blocks timing and Bus

2019-04-08 Thread Leandro Echevarría via USRP-users
Hi Xingjian, If I understood your problem correctly, you are expecting two equal streams to arrive at the same time on the output, but you have an AXI Crossbar in the middle. This is a packet-based router, so it is hard to predict its behavior timing-wise, and I don't think this would be the right

[USRP-users] Two RFNOC tx blocks timing and Bus

2019-04-08 Thread Xingjian Chen via USRP-users
Dear All, I am doing FPGA debugging with an E312. I have two exactly same signal generation RFNOC modules run simultaneously. The waveform is triggered by a reference clock generated in Verilog at the same time. What I found is that when the waveform went from RFNOC module to noc_block_radio_cor

Re: [USRP-users] UBX coherence between TX and RX

2019-04-08 Thread Piotr Krysik via USRP-users
Hi all, I looked at this thread and it reminded me of something. Once we purchased few X310 with UBX160 daughter-boards. One of them had some frequency offset on Tx channel, that decreased over time it was running, but very slowly. The daughter-board was then replaced by National Intruments (af

[USRP-users] RFNOC RX_Streamer example

2019-04-08 Thread Ran Lifshitz via USRP-users
Hi, I'm using UHD 3.14 with RFNOC implementation. I would like to switch from tcp sink stream (currently working) to a UHD rx stream. I'm not seeing any python example, and the only API i'm seeing in python is related to multiUSRP. Few questions: 1. What is the API and were I can get an example f