Hi, Recently I have been trying to figure out how to get the sample interval (in nanoseconds) on my USRP b205mini device that is coming from the radio IC. In regards with this, I would kindly ask you for assistance on the following questions:
1) While browsing the Verilog codes, I found out that a clock of 40MHz DDR is used for reading and writing to the AD9364 IC. When the “USRP Sink” block in GNU Radio is active, does it constantly poll at 40MHz? My initial intention was to write a separate counter block in Verilog to get the interval between the samples but if there are no stops/wait event on the bus, can I use this as time reference? 2) On the block diagram of the b205mini, it is mentioned that the DDC and the DUC are integrated in the FPGA. I have two questions here: - I couldn’t find them in the top module, so.. where is the exact location? - Is there some way to read the samples directly from the RF IC, before the DDC? 3) About the UHD interface – are there any examples on how to interface my own block with my own registers via the USB? Thanks in advance, Varban
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