Thanks, Jason. It's always nice to know I'm not alone.
It's also nice to know that Jonathan is around and replies very quickly.
Thanks for having our backs! 😁
Jeff
From: Jason
Sent: Wednesday, October 9, 2019 7:28 AM
To: Jonathon Pendlum ; Jeff S
Cc: usrp-user
-- Forwarded message -
От: Ivan Zahartchuk
Date: ср, 9 окт. 2019 г. в 06:05
Subject: Re: [USRP-users] Error handling D when reading data USRP N 210
To: Sam Reiter
CPU intel core i7 -3610QE 2.3 GGz
RAM 16 Gb
2 NIC intel 82574L gigabit ethernet and intel 82574LM gigabit ethernet
Hi guys,
I am looking to incorporate a channel equaliser and channel fader in the
DUC and DDC chain inside a B200. I can't find examples of this sort on
the Ettus KB. Is FPGA development confined to the X series and N series
devices?
Thanks very much.
BW
JS
__
Hi everyone,
We are currently trying to connect the N320 (configured with the XG image) to
one of our server using the QSFP+ interface through a switch (FS
S5900-24S4T2Q). The server is equipped with 40Gbps QSFP+ interface and the
connexion works when connecting directly by QSFP+ without the sw
Jeff,
This is an issue that tripped me up for numerous days in the past until
Jonathon pointed me to the same fix. It appears to be something wrong in
gr-ettus (or a combo of the change and the UHD you and I both used), but they
haven't seemed to have addressed this for some reason. It would
Jonathan,
I did what you suggested. Starting from scratch and for the record (because my
forgetful brain needs it and it may help someone else, or someone will point
out the errors of my ways):
$ git clone -b master https://github.com/EttusResearch/gr-ettus.git
$ cd gr-ettus
$ git checkout 498
