Re: [USRP-users] Fractional downsampling in rfnoc

Hello Jonathon I tried building the fractional downsampler again and was successful to build it in this version of UHD: UHD 4.0.0.rfnoc-devel-409-gec9138eb. Also there is a channelizer available at https://github.com/e33b1711/rfnoc-ppchan . But the problem with this channelizer is, it sends alm

Re: [USRP-users] Modifying RFNoC ddc block for 16 parallel instances

Hello Jonathon I need to use a sample rate between 20ksps to 1msps. Btw I tried following Brian's advice about breaking the logic. I was able to use to build a fpga image with 2x1:4 DDC block. Though I required 1:16 DDC block, but still it is great to start working. @Brian Padalino

[USRP-users] E310 with WIFI Dongle

Hi all, I am trying to connect my E310 (sg1) to the internet with a WIFI Dongle (rtl8192cu). Is there anyone knows how to connect the device to the network? I am using the sd image of http://files.ettus.com/e3xx_images/alpha/fido-test/ I followed the instructions below: Using this entry in /etc

[USRP-users] (no subject)

Hi all, I am trying to connect my E310 (sg1) to the internet with a WIFI Dongle (rtl8192cu). Is there anyone knows how to connect the device to the network? I am using the sd image of http://files.ettus.com/e3xx_images/alpha/fido-test/ I followed the instructions below: Using this entry in /etc

Re: [USRP-users] Modifying RFNoC ddc block for 16 parallel instances

Hi Snehasish, The DDC supports a wide range of sampling rates. Depending on the rates you want, some of the DDC filters could be removed to reduce utilization or there may be a better architecture to fit your situation. What rates do you need to support? Jonathon On Thu, Apr 23, 2020 at 3:19 AM

Re: [USRP-users] Cygwin build of E310_SG3

Hi Dan, Checkout UHD-3.15.LTS, which is the long term support tag for 3.15 and uses Vivado 2018.3. Also run "make cleanall" in the usrp3/top/e31x directory to remove any IP that may have been built with the wrong version (i.e. 2019.1). Jonathon On Tue, Apr 21, 2020 at 7:32 AM Harris, Dan via USR

Re: [USRP-users] using 'replay' block with 'duc'

Great. I forgot to mention that I was using an n310. On Thu, Apr 23, 2020 at 10:18 PM Wade Fife wrote: > Hi Rob, > > Thanks for the example! I'd take a look to see if I can reproduce the > issue and figure out what's going on. I've been working recently on the > Replay block, so I'm very interes

Re: [USRP-users] using 'replay' block with 'duc'

Hi Rob, Thanks for the example! I'd take a look to see if I can reproduce the issue and figure out what's going on. I've been working recently on the Replay block, so I'm very interested to understand what's going on. Thanks, Wade On Thu, Apr 23, 2020 at 1:36 PM Rob Kossler via USRP-users < usr

[USRP-users] using 'replay' block with 'duc'

Hi, I am having an issue with UHD 3.15.LTS using the replay block. When I play out my previously stored samples the first time, everything works fine. But after stopping the first time, if I try to start playing out again, I get a whole bunch of 'Lates' and no RF output. In order to duplicate the

[USRP-users] Download RFNoC image for usrp E310

Hello. I am using uhd 3.15 on the usrp e310 board. I want to run gr-phosphor but when flashing FPGA using uhd_image_loader --args type = e3xx --fpga-path / home / adray / rfnoc / src / uhd / fpga-src / usrp3 / top / e300 / build-E310_RFNOC_sg3 / e300.bit which is created by version uhd 3.14.1 and

Re: [USRP-users] Modifying RFNoC ddc block for 16 parallel instances

Hello Brian While writing the bitstream it gave an error stung the current design didn’t satisfy the timing constraint. I tried creating 12 blocks of DDC 1 to 2, blocks but that failed too saying the placer couldnot place more than 5% of the movable instances in the design. Regards Snehasish