Hi,
I am seeing something strange with timespecs. I am trying to test a single
RFNoC block on a device similar to the way in which a testbench tests a
single block in simulation. So, my rfnoc graph looks like "host_tx =>
block => host_rx". The issue I'm seeing is that the timespec in the rx
Hello. Tell me how to compile RFnoC firmware for USRP E310 so that you can
control GPIO through the Radio block?
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Hi all,
when using 3 X310 USRPs (TwinRX, UHD 3.15 LTS) synchronized via the CDA-2990
Octoclock (10MHz Ref and PPS distributed with length-matched cables), we are
observing deviations of up to two samples (e.g. one board late, one early)
between the individual devices.
We are seeing these
