HI Maria,
Rfnocmodtool does not support multiple inputs / outputs. You'll need to
edit the generated yaml file and use it with the utility
rfnoc_create_verilog to generate the block and noc shell. See
https://kb.ettus.com/RFNoC_4_Migration_Guide#Generating_a_Custom_Noc_Shell.
To edit the yaml file
On 01/20/2021 05:34 PM, Spam Blocker via USRP-users wrote:
We have an application that requires about 640Mbps of transmit and
640Mbps of receive samples bandwidth. We have a high performance
Dell laptop hooked to a B205.
Questions:
1. Do the different versions of UHD support different thro
We have an application that requires about 640Mbps of transmit and 640Mbps
of receive samples bandwidth. We have a high performance Dell laptop
hooked to a B205.
Questions:
1. Do the different versions of UHD support different throughput rates?
2. Are there maximum sample rates for the B205 that
By the way, I have created a block controller for every UHD4 RFNOC block
that I have created and I simply compile them in-tree since I don't know
how to make this work OOT. This has the nice advantage that uhd_usrp_probe
can then know about my blocks.
Rob
On Wed, Jan 20, 2021 at 4:46 PM Rob Koss
Hi Cédric,
I don't see anything wrong. Given that you said the FFT block works but
your block doesn't, could it be something related to a c++ block
controller?
Attached is a program I use to test an individual block with the graph
"host => block => host". It might help to see if this works. Thi
Hi,
We just received a USRP-2974 and would like to start working with
RFNoC/GNURadio (rather than LabView). I was hoping that somebody could
direct me to a reference for configuring this SDR for RFNoC/GNURadio.
There's a lot of material that covers non-embedded USRPs, but my
understanding is
Hi,
I'm trying to build an FPGA for the E320. I'm new to Ettus products and RFNoC
so this is my attempt.
I'm working with UHD 4.0.0.0 and have been following the tutorial from the 2020
GNU radio conference, RFNoC 4 Workshop.
I've used rfmodtool to create a new OOT folder structure. I've then u
Hi all,
Is it possible to automatically create an rfnoc_block schema with, for
example, 2 inputs and 2 outputs payload stream packets as in the addsub
blockdata using rfnocmodtool?
I can generate it using rfnoc_create_verilog.py through a block.yml file
following the steps in :
https://kb.ettus.co
Hi community,
I have some problems when trying to add VHDL processing module to RFNoC
block.
After inserted my VHDL module by the way described in addsub library
module, I tried to run "*make rfnoc_block_Demodulation1_tb*" command and
the output looks like the image below.
[image: image.png]
Do
