[USRP-users] Re: The design did not satisfy timing constraints.

On 22/12/2022 20:11, AERMAN TUERXUN. wrote: Hi, I am building a custom RFNoC block on USRP X310. When I was trying to build bitstream, after almost two hours processing, it gave me the error as below. Do you have any idea what timing constraints are? Is that because the custom IP is too large

[USRP-users] The design did not satisfy timing constraints.

Hi, I am building a custom RFNoC block on USRP X310. When I was trying to build bitstream, after almost two hours processing, it gave me the error as below. Do you have any idea what timing constraints are? Is that because the custom IP is too large for FPGA? Thank you! It started after [01:58:3

[USRP-users] Re: RFNoC Block Controller with Fractional Sample Rates

Hi Brian, The DDC has an extra variable, decim, which makes it a little more complicated, but I think you just need to have input and output rate resolvers such that if the input rate is set (perhaps property propagation from the rx radio), then the output rate will get properly resolved. And, the