I am trying to figure out the right way to use the clocks in RFNoC and the
clock domains. Referencing here:
https://kb.ettus.com/Getting_Started_with_RFNoC_in_UHD_4.0#Example:_Adding_an_FFT_Block
The tutorial says the X3XX has a `ce` clock of 214. 286 MHz, a `rfnoc_chdr`
clock of 200 MHz, and t
I am very active in developing firmware using Simulink and HDL Coder for this.
So far I wrap the Ettus noc shell as a black box and design my dsp firmware
around that.
It is fairly straightforward. The Ettus testbenches are happy, but now just
struggling with makefile issues for the main usrp i
On 08/02/2023 11:12, Melissa Lind wrote:
I needed to do some 5G work with MATLAB's 5G Toolbox, and was
wondering if someone could clarify:
https://www.mathworks.com/hardware-support/usrp.html claims:
N300 series from Ettus Research LLC
https://www.mathworks.com/hardware-support/ni-usrp-radios.
I needed to do some 5G work with MATLAB's 5G Toolbox, and was wondering if
someone could clarify:
https://www.mathworks.com/hardware-support/usrp.html claims:
N300 series from Ettus Research LLC
https://www.mathworks.com/hardware-support/ni-usrp-radios.html claims:
seems to have a picture of an N
I am currently trying to trace through the makefiles to see what is wrong, but
it seems it can not find any sources unless explicitly told. I could go through
the process of manually including every file needed, however, I feel like this
would be inefficient in the long run, so I am still trying
My initial guess was that the module in rfnoc_block_trigger.v wasn't named
rfnoc_block_trigger. Vivado says it found the file "rfnoc_block_trigger.v"
but not the module named "rfnoc_block_trigger". Or perhaps there was
something else wrong with the module that caused it to not compile? But
then I d
