However, I cant tell you that the AGC on B2x0 devices is controlled
> via
> > software (using set_rx_agc()). There is no need to directly modify
> the
> > state of any pins of the FPGA.
> >
> > I vaguely remember that there was a bug in an earlier version of
&
of gr-uhd
> (somewhere in 3.7) that made it difficult to turn on the AGC using GRC.
> That particular one is fixed in gr-uhd. Not sure about gr-ettus, though.
>
> Maybe try using set_rx_agc() manually in you flow-graph (*.py) and see
> if that helps.
>
> Cheers,
> Julian
>
Hi all,
I was wondering if it is possible to enable AGC from the RFNoC radio block
in GNURadio. I use UHD 4.0 version and GNURadio 3.8 with gr-ettus.
I see that the RFNoC Rx radio block has an enable/disable/default AGC
option in the GNURadio block which I assume calls the UHD function
Also, as you've noticed, the generated yaml file has the wrong interface,
> "fpga_iface: axis_data" should be "fpga_iface: axis_pyld_ctxt". That is a
> known issue that is in the pipeline to be fixed.
>
> Jonathon
>
> On Wed, Jan 20, 2021 at 8:18 AM Maria Muñoz v
Hi all,
Is it possible to automatically create an rfnoc_block schema with, for
example, 2 inputs and 2 outputs payload stream packets as in the addsub
blockdata using rfnocmodtool?
I can generate it using rfnoc_create_verilog.py through a block.yml file
following the steps in :
Hi all,
I have tried to install a custom OOT RFNoC block created using the
rfnocmodtool.
I've successfully created a module with my custom block, modifying the
verilog file created by the tool (
*rfnoc-test/rfnoc/fpga/rfnoc_block_myblock/rfnoc_block_myblock.v*) to
include the top level of my
;> I attach the modified YAML file.
>> I guess this can be related to the BSP connection part of the file but
>> I'm not sure how to change this part to do what I want to do. Is there any
>> documentation about this part of the yaml file? I have read the "Getting
>>
hey will be driven
>>> to 0 by default. 0 is often the right value for something that's unused,
>>> but not always. There may also be software implications.
>>>
>>> By the way, these kinds of changes are easier to make in UHD 4.0 since
>>> it's described by
e kinds of changes are easier to make in UHD 4.0 since
> it's described by a YAML file. So it's easy to say you just want one radio
> and to leave out the DDC/DUC, or DRAM FIFO, for example. The required
> Verilog is then generated by rfnoc_image_builder.
>
> Thanks,
>
>
Hi everyone,
I'm using an USRP E320 using the RFNoC image to implement a code that
requires too much FPGA resources. I only need to use one of the channels of
the USRP so I was wondering if it could be possible to eliminate the logic
associated with the other channel to save resources on the FPGA
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