Hi all,
Just a quick question, everything done using the UHD C++ and GNU Radio
Companion, is it done in the FPGA or computer itself? I am using USRP B210 and
what is the FPGA used for, as I know Gnu Radio is a software-defined-radio
framework, and all the blocks execute on the PC host.
Thank y
Hi all,
Theoretically, in frequency domain, the spectrum for SQUARE wave should be a
SINC and for the spectrum of RAMP wave should be decreasing with every odd
harmonics. A question that I want to ask is, will I get to see these frequency
spectrum in the Spectrum Analyzer after being transmitt
ated data (with a File Source block). You can also push down some of
your DSP logics to the FPGA of the USRPs, if you have licences for the needed
software (and if you are okay with HDL).
Regards,
Kyeong Su Shin
________
보낸 사람: Yeo Jin Kuang Alvin (IA) via USRP-use
Hi all,
I am getting underruns and overruns when trying to run the UHD programs, both
GNU radio and C++. The maximum my computer can handle is 4MHz sampling rate
before seeing "U".
I've searched online and most people say, change a new computer into quad core
etc.
Are there any other ways
ol custom programming
registers in the USRP.
YMMV, remember this is a suggestion, custom changes to the FPGA don’t have any
support.
-Ian
On May 2, 2018, at 2:14 AM, Yeo Jin Kuang Alvin (IA) via USRP-users
mailto:usrp-users@lists.ettus.com>> wrote:
Hi,
Thanks for the reply!
If lets say
ypass them.
My apologies if I've missed this in another email, but what is your goal with
these changes?
Regards,
Derek
On Thu, Apr 26, 2018 at 10:18 AM, Yeo Jin Kuang Alvin (IA) via USRP-users
mailto:usrp-users@lists.ettus.com>> wrote:
Hi everyone!
For the FPGA source code written for
Hi all,
I have tried the tx_waveforms example and measured it using a spectrum analyser
(SA). However, no matter what input wave-type I chose, I will get the same
output seen in the SA. For example, when I chose SINE and a center frequency of
100MHz, I observed spectrums at 100, 300, 500 ,700 ,
g point. Most of what
you need is already there, its just up to you to calculate the samples needed
to generate the chirp and put them into the tx buffer.
https://github.com/EttusResearch/uhd/blob/maint/host/examples/tx_bursts.cpp
I'm happy to help if you have any specific questions on this.
Hi all,
As the title mentioned, what is the difference between master_clock_rate and
rate in UHD? Which one is the DAC's sampling rate? I'm using USRP B210.
Thank you in advance!
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ges to the UHD driver to
remove support for those features if you bypass them.
My apologies if I've missed this in another email, but what is your goal with
these changes?
Regards,
Derek
On Thu, Apr 26, 2018 at 10:18 AM, Yeo Jin Kuang Alvin (IA) via USRP-users
mailto:usrp-users@lists.et
Hi everyone!
For the FPGA source code written for b210, I noticed that the input to the
GPIF_D that is 32 bits, and then in went through some FIFOs up converting to 64
bits and then down to 12 bits output (tx_codec_d).
May I know what is the purpose of up converting and then down convert again?
the tx buffer.
https://github.com/EttusResearch/uhd/blob/maint/host/examples/tx_bursts.cpp
I'm happy to help if you have any specific questions on this.
-Trip
From: USRP-users
mailto:usrp-users-boun...@lists.ettus.com>>
On Behalf Of Yeo Jin Kuang Alvin (IA) via USRP-users
Sent: Monday,
Hi all,
Does anyone know how to create a chirp signal using UHD C++? Are there any code
examples and which files do I need?
Thanks in advance!
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Hi all,
I would like to download Open Source UHD because I want to edit some files like
the AD9361.cpp files.
I am currently using: Cmake 3.11.1 ; Visual Studio Express 2015; Boost_1_67_0;
LibUSB-1.0.21; Python 2.7; Mako; UHD_3.10.1.1_release;
I followed the steps in
https://kb.ettus.com/Buil
Hi all,
I followed the ettus research guide
https://kb.ettus.com/Building_and_Installing_the_USRP_Open_Source_Toolchain_(UHD_and_GNU_Radio)_on_Windows
and start building the *ALL_Build* file. The error I keep getting is LNK1181
cannot open input file '..\lib\Release\uhd.lib' . I checked the fol
Hi all,
I need to control the AD9361 in the USRP board and I have the AD93611_ctrl.cpp
code.
The question is if I can just build the ad9361_ctrl.cpp and run the .exe file
to control it in the board (Not sure if it will send to the AD9361 in the
board) or must I build a certain top file that i
Hi all,
I have two questions regarding the USRP B210 configurations using API and FPGA
at the same time.
1) USRP FPGA Source Code:
I have used the Xilinx DDS Compiler using the Coregen and generated out a chirp
signal using 2 phase accumulator followed by a SIN_LUT. However, I don't know
Hi all,
I am currently using USRP B210 and I would like to generate a chirp signal
using DDS in the FPGA, I have uploaded the source code by ettus into ISE 14.7.
But I am not sure which input and output pin of the code to use, as I have to
control the input for the desired chirp signal. Any he
ail.com>]
Sent: Thursday, 12 April 2018 9:39 AM
To: Yeo Jin Kuang Alvin (IA)
Cc: usrp-users@lists.ettus.com<mailto:usrp-users@lists.ettus.com>
Subject: Re: [USRP-users] AD9361 in USRP B210
What exactly do you want to do?
On Wed, Apr 11, 2018 at 6:33 PM Yeo Jin Kuang Alvin (IA) via USRP-use
ed, Apr 11, 2018 at 6:33 PM Yeo Jin Kuang Alvin (IA) via USRP-users
mailto:usrp-users@lists.ettus.com>> wrote:
Hi all,
How do we set up the Ad9361_driver and ad9361 controls in the
uhd/host/lib/usrp/common file for Ubuntu? What are the steps and
ts.ettus.com<mailto:usrp-users@lists.ettus.com>
Subject: Re: [USRP-users] AD9361 in USRP B210
What exactly do you want to do?
On Wed, Apr 11, 2018 at 6:33 PM Yeo Jin Kuang Alvin (IA) via USRP-users
mailto:usrp-users@lists.ettus.com>> wrote:
Hi all,
How do we set up the Ad9361_driver and ad9
: Thursday, 12 April 2018 9:39 AM
To: Yeo Jin Kuang Alvin (IA)
Cc: usrp-users@lists.ettus.com
Subject: Re: [USRP-users] AD9361 in USRP B210
What exactly do you want to do?
On Wed, Apr 11, 2018 at 6:33 PM Yeo Jin Kuang Alvin (IA) via USRP-users
mailto:usrp-users@lists.ettus.com>> wrote:
Hi all,
Hi all,
How do we set up the Ad9361_driver and ad9361 controls in the
uhd/host/lib/usrp/common file for Ubuntu? What are the steps and prerequisites
for this?
Thank you in advance!
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Hi everyone,
I want to control the AD9361 in USRP B210 using external host, how can I do it?
What are the steps and procedures I have to do?
I am using Xilinx ISE 14.7 and Ubuntu.
Thanks in advance!
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Hi everyone,
I tried to build the USRP B210 FPGA for Xilinx ISE 14.7 (Windows) and I got
this in my cmd prompt:
C:\Users\WORK\Desktop\fpga-maint\usrp3\top\b200>make B210 PROJECT_ONLY=1
"ISE Version: Release 14.7 - xtclsh P.20131013 (nt64)"
make -f Makefile.b200.inc proj NAME=B210 DEVICE=XC6SLX15
ee/maint/usrp3/lib
-Robin
On Mon, Apr 9, 2018 at 10:59 AM, Yeo Jin Kuang Alvin (IA) via USRP-users
mailto:usrp-users@lists.ettus.com>> wrote:
Hi everyone,
I want to use the ettus code for the USRP B210, however, may I know which is
the Top file as I noticed there are 3 different o
Hi everyone,
I want to use the ettus code for the USRP B210, however, may I know which is
the Top file as I noticed there are 3 different ones. B200.v , B200_core.v ,
B200_io.v. Tried to add the source file to Xilinx ISE 14.7 but there are some
files that I couldn't find, eg. Gpif_sync, slave_f
host. There is a *lot* of configuration
functionality that needs to be captured.
Are the constraints of your project such that you are not allowed to have a
host connected to USB?
On Apr 5, 2018, at 7:57 PM, Yeo Jin Kuang Alvin (IA) via USRP-users
mailto:usrp-users@lists.ettus.com>>
ficant
as starting a transmit stream and/or controlling the AD9361 in some way. We'll
need much more detail in order to be able to help further. What changes did you
make to the FPGA? What exactly are you trying to do overall?
--Neel Pandeya
On 5 April 2018 at 18:07, Yeo Jin Kuang Alvin (IA) v
Hi everyone,
I have tried to program the Spartan 6 FPGA using Xilinx 14.7 to send out a
signal and to control the AD9361. However, I couldn't get an output out from
the transmitter. Can I just solely on FPGA or must I use the API for the USRP
B210? What are the steps and procedures I have to do
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