Re: [USRP-users] Advise on how to modifying HDL design E310 to add custom blocks

Great, thank you for the clarification, Derek. Regards, Brais. 2017-10-26 17:58 GMT+02:00 Derek Kozel : > Hello Brais, > > Sorry for the long delay. Yes, the B210 has a Spartan 6 which is not > supported by Vivado so the design uses ISE. This, and the smaller size of > the B210's FPGA, is why

Re: [USRP-users] Advise on how to modifying HDL design E310 to add custom blocks

Hello Brais, Sorry for the long delay. Yes, the B210 has a Spartan 6 which is not supported by Vivado so the design uses ISE. This, and the smaller size of the B210's FPGA, is why RFNoC support has not been added to it. All third generation USRPs support RFNoC and so will all planned future USRPs.

Re: [USRP-users] Advise on how to modifying HDL design E310 to add custom blocks

Thank you Derek, I was playing around with E300 design, but we actually need to use B2X0 devices, apparently not supported by RFNoC. Also we need to implement some complex decimation and filtering so that FIR block will not be enough. I guess, if I'm not mistaken, our only choice is to use Xilinx

Re: [USRP-users] Advise on how to modifying HDL design E310 to add custom blocks

Hello Brais, The HDL design does have a top block and is composed of usefully divided sub blocks. It is not however designed using the graphical Vivado workflow, but a source based one. Here is the top block: https://github.com/EttusResearch/fpga/blob/maint/usrp3/top/e300/e310.v Your application

[USRP-users] Advise on how to modifying HDL design E310 to add custom blocks

Hello, We want to add some blocks to HDL design in E310 device. We followed the instructions to build Vivado project and it worked okay. Thing is the built design when opened in Vivado looks this way ... where design sources hiera