[USRP-users] Re: How can I define a global reg variable in Verilog between RFNOC blocks?

On Mon, Nov 7, 2022 at 6:29 PM Marcus Müller wrote: > Hi sp, > > That sounds like a bad idea. How are you planning to synchronize access to > that register? > > Generally, in almost *any* context, avoid global state. That makes things > complicated and > error prone; this is true for python as

[USRP-users] Re: How can I define a global reg variable in Verilog between RFNOC blocks?

Thanks very much, Marcus. Can explain more? I had not any idea how develop your way? On Mon, Nov 7, 2022 at 11:29 PM Marcus Müller wrote: > Hi sp, > > That sounds like a bad idea. How are you planning to synchronize access to > that register? > > Generally, in almost *any* context, avoid global

[USRP-users] Re: How can I define a global reg variable in Verilog between RFNOC blocks?

Hi, I tested your way but I have challenges with it. I described it in the below link. do you have any offer? Thanks very much https://lists.ettus.com/empathy/thread/A65LFSBUISOLPBGIRJWSJYBESRPMPEPC On Mon, Aug 1, 2022 at 1:47 PM Paolo Palana wrote: > For experimental purpose I did something

[USRP-users] Re: How can I define a global reg variable in Verilog between RFNOC blocks?

For experimental purpose I did something like you say. Referring to usrp X300 1. add the reg variable to rfnoc_ce_default_inst_x300.v (or the relevant file for your radio) 2. add to the noc _block module declaration an additional input port e.g. module noc_test #(   parameter NOC_ID =