On 23/02/2023 16:39, Maxim Belotserkovsky wrote:
Hi. I'm doing initial verification of a B200. A sine wave at 100MHz is
fed into front end. The receiver is configured to use its quadrature
downconverter to bring the wave down to 100kHz, which is then sampled
by a GR "USRP Source" component and displayed in a "Frequency Sink"
GUI. I notice the following unexplained behavior: as long as I set the
Sampling Rate parameter of the radio to anything > or equal to 200 kHz
(i.e. more than twice the frequency of the analog tone I'm trying to
sample) I see the tone in the FFT output where I expect it to be;
however, any sampling frequency less than that, and I get no output at
all. For example, with the 100kHz tone in my experiment, setting the
sampling rate to 100kHz should result in a spectral line near DC,
however, no output is observed. It is almost as if there is something
going on behind the scenes that doesn't allow for aliasing to happen,
either in the stock FPGA design or some other block external to the
FPGA. Can anyone comment? I just want to conduct a very basic sanity
check of the received down-conversion and sampling. Is there a
functional description of the digital and analog processing chain that
B200 comes from the factory with? Thanks
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Most of the signal processing in a B200 is done by the AD9361 RF
front-end chip. There is still a DDC in the FPGA, to handle
cases where the AD9361 can't do all the job. If you ask for
100ksps (quite low for the B200), the job of delivering that
bandwidth to the host will be shared between the AD9361 and the DDC
in the FPGA. The combined filter roll-off of those
is going to be quite aggressive--this is pretty normal for SDRs.
The datasheets for the AD9361 are available freely, as is the source
code for all of UHD and the firmware and FPGA for
the B2xx series.
Here's the basic summary of what happens:
The AD9361 chip arranges to deliver a complex-baseband (ZeroIF)
sample stream to the FPGA at some sample-rate
(that is often some multiple of the target sample rate). The FPGA
then uses its DDC implementation to bring the
signal down to the lower sample rate, and PART OF THAT PROCESS
inherently involves filtering. That is then
delivered to the host as a complex baseband signal. UHD has code
that knows how to configure the AD9361
and FPGA elements to deliver what you asked for--including
knowledge of what the minimum tuning granularity
of the AD9361 is, so that it can tell the DDC to rotate the signal
down to baseband first if necessary.
There are flourishes and nuances of course--there's analog gain blocks
involved, quadrature I/Q balancing algorithms in
the AD9361, etc. The inside of the AD9361 is itself quite complex,
and I think you'd need to get the "developer docs"
to get all the information on how it works--but I think that's free
and easy to get.
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