Yes, for the 200 MHz bitstreams there is a 2x decimation filter in
rf_core_200:
https://github.com/EttusResearch/uhd/blob/master/fpga/usrp3/top/x400/rf/200m/rf_core_200m.v#L184
There's also a 3x decimation filter in adc_400m_bd.tcl:
On Wed, Mar 22, 2023 at 10:40 PM Wade Fife wrote:
> Hi Brian,
>
> Unfortunately, the DSP inside the current RFNoC DDC block processes one
> sample per clock cycle. So the maximum sample rate through the DDC is the
> same as the rate of the clock you provide to the ce clock input. With the
> 400
Hi Brian,
Unfortunately, the DSP inside the current RFNoC DDC block processes one
sample per clock cycle. So the maximum sample rate through the DDC is the
same as the rate of the clock you provide to the ce clock input. With the
400 MHz bitstreams, radio_2x is 245.76 MHz. Because this is below
