I've built up a custom FPGA based on the 400 MHz image, and I have a bit of an asymmetric scenario going on here. The TX side of things has a custom block and it feeds the TX port at 491.52 MHz.
The RX side I only need to receive at 30.72 Msps, so I instantiate a 2-channel DDC and connect it statically: - radio0/out_0 -> ddc0/in_0, ddc0/out_0 -> ep0/in0 - radio0/out_1 -> ddc0/in_1, ddc0/out_1 -> ep1/in0 When I set up my clock domains, I noticed there was a mix between the different setups, so I went with radio_2x for the DDC: - srcport: radio, dstblk: radio0, dstport: radio - srcport: raio_2x, dstblk: ddc0, dstport: ce This is how the X410_200 image seems to do it, so I figured it'd be fine. When I try to receive at the sample rate, I immediately get an overflow. To test it's just the FPGA being problematic, I set the program to receive from radio 1 which doesn't use the DDC and I receive the appropriate 491.52 Msps with no overflows. So my question is why is adding the DDC problematic? The only other difference I can see is the CHDR_WIDTH is 512 for my image and 64 for the X410_100 and X410_200 images? Any insight would be useful and welcome. Thanks, Brian
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