On 2015/08/19 02:55:32, Srikumar wrote:
mailto:sbo...@nvidia.com changed reviewers:
+ mailto:ar...@nvidia.com
LGTM
https://codereview.chromium.org/1287173004/
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PTAL
https://codereview.chromium.org/797233002/diff/11/src/base/cpu.cc
File src/base/cpu.cc (right):
https://codereview.chromium.org/797233002/diff/11/src/base/cpu.cc#newcode303
src/base/cpu.cc:303: variant_(0),
On 2014/12/19 06:32:09, Benedikt Meurer wrote:
The 0 default is not safe a
PTAL
https://codereview.chromium.org/797233002/
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Addressed the new comment from rmcilroy. PTAL
I used git commit --amend to update the commit message and that did not
reflect
here when I next did git cl upload. I had to do git-cl description and git
cl
upload and then it worked.
JF,
I just now noticed that I left out one comment of yours.
Addressed all your comments.
PTAL
https://codereview.chromium.org/797233002/diff/1/src/arm/assembler-arm.cc
File src/arm/assembler-arm.cc (right):
https://codereview.chromium.org/797233002/diff/1/src/arm/assembler-arm.cc#newcode133
src/arm/assembler-arm.cc:133: supported_ |= 1u << COHERENT_CACH
On 2014/12/15 16:23:24, JF wrote:
Is it guaranteed that all Denver CPUs will have coherent caches? I'd like
to
make sure that this code is still correct when Denver 5 comes out and
everyone
forgot that this code is avoiding I$ fushes.
In the long term, there should be an API to export this
Reviewers: JF, rmcilroy,
Message:
On 2014/12/15 04:59:39, arajp wrote:
mailto:ar...@nvidia.com changed reviewers:
+ mailto:j...@chromium.org, mailto:rmcil...@chromium.org
JFB,
This is the same patch I took over from Srikumar since he is on a long
vacation.
PTAL.
Description:
Make
