Patchset 7 (id:??) landed as
https://crrev.com/f4fb7025691ffa17fd36390e116461c0c6a886f1
Cr-Commit-Position: refs/heads/master@{#25898}
https://codereview.chromium.org/797233002/
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Committed patchset #7 (id:120001)
https://codereview.chromium.org/797233002/
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CQ is trying da patch. Follow status at
https://chromium-cq-status.appspot.com/patch-status/797233002/120001
https://codereview.chromium.org/797233002/
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LGTM, thanks.
https://codereview.chromium.org/797233002/
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PTAL
https://codereview.chromium.org/797233002/diff/11/src/base/cpu.cc
File src/base/cpu.cc (right):
https://codereview.chromium.org/797233002/diff/11/src/base/cpu.cc#newcode303
src/base/cpu.cc:303: variant_(0),
On 2014/12/19 06:32:09, Benedikt Meurer wrote:
The 0 default is not safe a
> I just now noticed that I left out one comment of yours. Did you mean
to say
> updating variant_ through CPUID is a better way than through
ExtractField()?
> Should I change that also?
I'd rather have all CPUs contain valid data for variant_, not just ARM.
CPUID
seems the right way to d
I used git commit --amend to update the commit message and that did not
reflect
here when I next did git cl upload. I had to do git-cl description and
git cl
upload and then it worked.
Oh there's an edit button on the web page that'll work next time.
I just now noticed that I left out one c
Getting close, final comments.
https://codereview.chromium.org/797233002/diff/11/src/base/cpu.cc
File src/base/cpu.cc (right):
https://codereview.chromium.org/797233002/diff/11/src/base/cpu.cc#newcode303
src/base/cpu.cc:303: variant_(0),
The 0 default is not safe as we would default to
PTAL
https://codereview.chromium.org/797233002/
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Addressed the new comment from rmcilroy. PTAL
I used git commit --amend to update the commit message and that did not
reflect
here when I next did git cl upload. I had to do git-cl description and git
cl
upload and then it worked.
JF,
I just now noticed that I left out one comment of yours.
You're still missing some of the comments, and the update on the CL
description.
https://codereview.chromium.org/797233002/
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On 2014/12/18 14:05:07, rmcilroy wrote:
https://codereview.chromium.org/797233002/diff/20001/src/arm64/assembler-arm64.cc
File src/arm64/assembler-arm64.cc (right):
https://codereview.chromium.org/797233002/diff/20001/src/arm64/assembler-arm64.cc#newcode63
src/arm64/assembler-arm64.cc:63: vo
https://codereview.chromium.org/797233002/diff/20001/src/arm64/assembler-arm64.cc
File src/arm64/assembler-arm64.cc (right):
https://codereview.chromium.org/797233002/diff/20001/src/arm64/assembler-arm64.cc#newcode63
src/arm64/assembler-arm64.cc:63: void CpuFeatures::PrintFeatures() { }
Please u
Addressed all your comments.
PTAL
https://codereview.chromium.org/797233002/diff/1/src/arm/assembler-arm.cc
File src/arm/assembler-arm.cc (right):
https://codereview.chromium.org/797233002/diff/1/src/arm/assembler-arm.cc#newcode133
src/arm/assembler-arm.cc:133: supported_ |= 1u << COHERENT_CACH
On 2014/12/15 16:23:24, JF wrote:
Is it guaranteed that all Denver CPUs will have coherent caches? I'd like
to
make sure that this code is still correct when Denver 5 comes out and
everyone
forgot that this code is avoiding I$ fushes.
In the long term, there should be an API to export this
https://codereview.chromium.org/797233002/diff/1/src/arm64/assembler-arm64.cc
File src/arm64/assembler-arm64.cc (right):
https://codereview.chromium.org/797233002/diff/1/src/arm64/assembler-arm64.cc#newcode48
src/arm64/assembler-arm64.cc:48: supported_ = 0;
On 2014/12/15 16:23:23, JF wrote:
The
Could you also update the description of the patch to explain why this is a
significant perf gain (avoid syscall on ARM) and what the performance
numbers
look like after this patch.
https://codereview.chromium.org/797233002/
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Is it guaranteed that all Denver CPUs will have coherent caches? I'd like to
make sure that this code is still correct when Denver 5 comes out and
everyone
forgot that this code is avoiding I$ fushes.
https://codereview.chromium.org/797233002/diff/1/src/arm64/assembler-arm64.cc
File src/arm64
https://codereview.chromium.org/797233002/diff/1/src/arm/assembler-arm.cc
File src/arm/assembler-arm.cc (right):
https://codereview.chromium.org/797233002/diff/1/src/arm/assembler-arm.cc#newcode133
src/arm/assembler-arm.cc:133: supported_ |= 1u << COHERENT_CACHE;
Nit: Add { and } for block.
htt
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