On Fri, Jan 14, 2022 at 05:33:58PM +0100, Cornelia Huck wrote:
> On Fri, Jan 14 2022, "Michael S. Tsirkin" wrote:
>
> > It is unfortunate that it does not copy this requirement in more places,
> > and that the non-conformance text is incomplete and does not
> > mention the MSI-X usage at all.
> >
On Fri, Jan 14 2022, "Michael S. Tsirkin" wrote:
> It is unfortunate that it does not copy this requirement in more places,
> and that the non-conformance text is incomplete and does not
> mention the MSI-X usage at all.
>
> I propose to extend 4.1.4.5 ISR status capability and
> 4.1.5.4 Notific
The spec says (v1.1 4.1.4.5 ISR status capability):
The VIRTIO_PCI_CAP_ISR_CFG capability refers to at least a single byte, which
contains the 8bit ISR
status field to be used for INT#x interrupt handling.
and
to avoid an extra access, simply reading this register resets it to 0 and
causes th
