The assumption that we have an overall irqs_pending flags,
and a one-to-one lguest <-> task mapping fails to hold on x86_64,
where we can have multiple puppies, aka vcpus.
Although ifdefs could be used, it makes the code much more
unreadable, and other ports are on the way, anyway. So some sort
of
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Hi Steven, Markus,
On 9/10/07, Steven Rostedt <[EMAIL PROTECTED]> wrote:
>
> --
> On Mon, 10 Sep 2007, Markus Armbruster wrote:
> >
> > I believe this possible, but unlikely (perhaps not so unlikely on
> > virtual machines). Scenarios involve enable succeeding the first
> > time, failing the seco
--
On Mon, 10 Sep 2007, Markus Armbruster wrote:
>
> I believe this possible, but unlikely (perhaps not so unlikely on
> virtual machines). Scenarios involve enable succeeding the first
> time, failing the second time, and succeeding the third time. I can
> provide details, but the point I'd lik
When enabling interrupts fails, the interrupt enable bit remains set
in i8042_ctr. Later writes of i8042_ctr to the hardware could
accidentally retry enabling interrupts. Clear the bit on failure.
Signed-off-by: Markus Armbruster <[EMAIL PROTECTED]>
Acked-by: Steven Rostedt <[EMAIL PROTECTED]>
