Modified: trunk/Source/_javascript_Core/ChangeLog (114433 => 114434)
--- trunk/Source/_javascript_Core/ChangeLog 2012-04-17 21:32:37 UTC (rev 114433)
+++ trunk/Source/_javascript_Core/ChangeLog 2012-04-17 21:41:17 UTC (rev 114434)
@@ -1,5 +1,24 @@
2012-04-17 Filip Pizlo <fpi...@apple.com>
+ DFG and LLInt should not clobber the frame pointer on ARMv7
+ https://bugs.webkit.org/show_bug.cgi?id=84185
+ <rdar://problem/10767252>
+
+ Reviewed by Gavin Barraclough.
+
+ Changed LLInt to use a different register. Changed DFG to use one fewer
+ registers. We should revisit this and switch the DFG to use a different
+ register instead of r7, but we can do that in a subsequent step since
+ the performance effect is tiny.
+
+ * dfg/DFGGPRInfo.h:
+ (GPRInfo):
+ (JSC::DFG::GPRInfo::toRegister):
+ (JSC::DFG::GPRInfo::toIndex):
+ * offlineasm/armv7.rb:
+
+2012-04-17 Filip Pizlo <fpi...@apple.com>
+
use after free in JSC::DFG::Node::op / JSC::DFG::ByteCodeParser::flushArgument
https://bugs.webkit.org/show_bug.cgi?id=83942
<rdar://problem/11247370>
Modified: trunk/Source/_javascript_Core/dfg/DFGGPRInfo.h (114433 => 114434)
--- trunk/Source/_javascript_Core/dfg/DFGGPRInfo.h 2012-04-17 21:32:37 UTC (rev 114433)
+++ trunk/Source/_javascript_Core/dfg/DFGGPRInfo.h 2012-04-17 21:41:17 UTC (rev 114434)
@@ -386,18 +386,17 @@
class GPRInfo {
public:
typedef GPRReg RegisterType;
- static const unsigned numberOfRegisters = 9;
+ static const unsigned numberOfRegisters = 8;
// Temporary registers.
static const GPRReg regT0 = ARMRegisters::r0;
static const GPRReg regT1 = ARMRegisters::r1;
static const GPRReg regT2 = ARMRegisters::r2;
static const GPRReg regT3 = ARMRegisters::r4;
- static const GPRReg regT4 = ARMRegisters::r7;
- static const GPRReg regT5 = ARMRegisters::r8;
- static const GPRReg regT6 = ARMRegisters::r9;
- static const GPRReg regT7 = ARMRegisters::r10;
- static const GPRReg regT8 = ARMRegisters::r11;
+ static const GPRReg regT4 = ARMRegisters::r8;
+ static const GPRReg regT5 = ARMRegisters::r9;
+ static const GPRReg regT6 = ARMRegisters::r10;
+ static const GPRReg regT7 = ARMRegisters::r11;
// These registers match the baseline JIT.
static const GPRReg cachedResultRegister = regT0;
static const GPRReg cachedResultRegister2 = regT1;
@@ -418,7 +417,7 @@
static GPRReg toRegister(unsigned index)
{
ASSERT(index < numberOfRegisters);
- static const GPRReg registerForIndex[numberOfRegisters] = { regT0, regT1, regT2, regT3, regT4, regT5, regT6, regT7, regT8 };
+ static const GPRReg registerForIndex[numberOfRegisters] = { regT0, regT1, regT2, regT3, regT4, regT5, regT6, regT7 };
return registerForIndex[index];
}
@@ -426,7 +425,7 @@
{
ASSERT(reg != InvalidGPRReg);
ASSERT(reg < 16);
- static const unsigned indexForRegister[16] = { 0, 1, 2, InvalidIndex, 3, InvalidIndex, InvalidIndex, 4, 5, 6, 7, 8, InvalidIndex, InvalidIndex, InvalidIndex, InvalidIndex };
+ static const unsigned indexForRegister[16] = { 0, 1, 2, InvalidIndex, 3, InvalidIndex, InvalidIndex, InvalidIndex, 4, 5, 6, 7, InvalidIndex, InvalidIndex, InvalidIndex, InvalidIndex };
unsigned result = indexForRegister[reg];
ASSERT(result != InvalidIndex);
return result;
