- Revision
- 222625
- Author
- fpi...@apple.com
- Date
- 2017-09-28 12:50:05 -0700 (Thu, 28 Sep 2017)
Log Message
Enable gigacage on iOS
https://bugs.webkit.org/show_bug.cgi?id=177586
Reviewed by Michael Saboff.
Source/bmalloc:
This enables Gigacage on iOS using a much smaller cage size. It's not necessary for it to be so
small, but this is a good conservative starting point to start to exercise the code.
* bmalloc/Gigacage.h:
Source/_javascript_Core:
The hardest part of enabling Gigacage on iOS is that it requires loading global variables whil
executing JS, so the LLInt needs to know how to load from global variables on all platforms that
have Gigacage. So, this teaches ARM64 how to load from global variables.
* offlineasm/arm64.rb:
* offlineasm/asm.rb:
* offlineasm/instructions.rb:
Modified Paths
Diff
Modified: trunk/Source/_javascript_Core/ChangeLog (222624 => 222625)
--- trunk/Source/_javascript_Core/ChangeLog 2017-09-28 19:35:10 UTC (rev 222624)
+++ trunk/Source/_javascript_Core/ChangeLog 2017-09-28 19:50:05 UTC (rev 222625)
@@ -1,3 +1,18 @@
+2017-09-28 Filip Pizlo <fpi...@apple.com>
+
+ Enable gigacage on iOS
+ https://bugs.webkit.org/show_bug.cgi?id=177586
+
+ Reviewed by Michael Saboff.
+
+ The hardest part of enabling Gigacage on iOS is that it requires loading global variables whil
+ executing JS, so the LLInt needs to know how to load from global variables on all platforms that
+ have Gigacage. So, this teaches ARM64 how to load from global variables.
+
+ * offlineasm/arm64.rb:
+ * offlineasm/asm.rb:
+ * offlineasm/instructions.rb:
+
2017-09-28 Mark Lam <mark....@apple.com>
Add missing exception checks and book-keeping for exception check validation.
Modified: trunk/Source/_javascript_Core/offlineasm/arm64.rb (222624 => 222625)
--- trunk/Source/_javascript_Core/offlineasm/arm64.rb 2017-09-28 19:35:10 UTC (rev 222624)
+++ trunk/Source/_javascript_Core/offlineasm/arm64.rb 2017-09-28 19:50:05 UTC (rev 222625)
@@ -260,6 +260,31 @@
newList
end
+def arm64LowerLabelReferences(list)
+ newList = []
+ list.each {
+ | node |
+ if node.is_a? Instruction
+ case node.opcode
+ when "loadi", "loadis", "loadp", "loadq", "loadb", "loadbs", "loadh", "loadhs"
+ labelRef = node.operands[0]
+ if labelRef.is_a? LabelReference
+ tmp = Tmp.new(node.codeOrigin, :gpr)
+ newList << Instruction.new(codeOrigin, "globaladdr", [LabelReference.new(node.codeOrigin, labelRef.label), tmp])
+ newList << Instruction.new(codeOrigin, node.opcode, [Address.new(node.codeOrigin, tmp, Immediate.new(node.codeOrigin, labelRef.offset)), node.operands[1]])
+ else
+ newList << node
+ end
+ else
+ newList << node
+ end
+ else
+ newList << node
+ end
+ }
+ newList
+end
+
# Workaround for Cortex-A53 erratum (835769)
def arm64CortexA53Fix835769(list)
newList = []
@@ -296,6 +321,7 @@
result = riscLowerHardBranchOps64(result)
result = riscLowerShiftOps(result)
result = arm64LowerMalformedLoadStoreAddresses(result)
+ result = arm64LowerLabelReferences(result)
result = riscLowerMalformedAddresses(result) {
| node, address |
case node.opcode
@@ -904,6 +930,15 @@
$asm.putStr("#if CPU(ARM64_CORTEXA53)")
$asm.puts "nop"
$asm.putStr("#endif")
+ when "globaladdr"
+ uid = $asm.newUID
+ $asm.puts "L_offlineasm_loh_adrp_#{uid}:"
+ $asm.puts "adrp #{operands[1].arm64Operand(:ptr)}, #{operands[0].asmLabel}@GOTPAGE"
+ $asm.puts "L_offlineasm_loh_ldr_#{uid}:"
+ $asm.puts "ldr #{operands[1].arm64Operand(:ptr)}, [#{operands[1].arm64Operand(:ptr)}, #{operands[0].asmLabel}@GOTPAGEOFF]"
+ $asm.deferAction {
+ $asm.puts ".loh AdrpLdrGot L_offlineasm_loh_adrp_#{uid}, L_offlineasm_loh_ldr_#{uid}"
+ }
else
lowerDefault
end
Modified: trunk/Source/_javascript_Core/offlineasm/asm.rb (222624 => 222625)
--- trunk/Source/_javascript_Core/offlineasm/asm.rb 2017-09-28 19:35:10 UTC (rev 222624)
+++ trunk/Source/_javascript_Core/offlineasm/asm.rb 2017-09-28 19:50:05 UTC (rev 222625)
@@ -46,6 +46,8 @@
@codeOrigin = nil
@numLocalLabels = 0
@numGlobalLabels = 0
+ @deferredActions = []
+ @count = 0
@newlineSpacerState = :none
@lastlabel = ""
@@ -73,10 +75,23 @@
putsProcEndIfNeeded
end
putsLastComment
+ @deferredActions.each {
+ | action |
+ action.call()
+ }
@outp.puts "OFFLINE_ASM_END" if !$emitWinAsm
@state = :cpp
end
+ def deferAction(&proc)
+ @deferredActions << proc
+ end
+
+ def newUID
+ @count += 1
+ @count
+ end
+
def inAsm
enterAsm
yield
Modified: trunk/Source/_javascript_Core/offlineasm/instructions.rb (222624 => 222625)
--- trunk/Source/_javascript_Core/offlineasm/instructions.rb 2017-09-28 19:35:10 UTC (rev 222624)
+++ trunk/Source/_javascript_Core/offlineasm/instructions.rb 2017-09-28 19:50:05 UTC (rev 222625)
@@ -267,7 +267,8 @@
ARM64_INSTRUCTIONS =
[
"pcrtoaddr", # Address from PC relative offset - adr instruction
- "nopFixCortexA53Err835769" # nop on Cortex-A53 (nothing otherwise)
+ "nopFixCortexA53Err835769", # nop on Cortex-A53 (nothing otherwise)
+ "globaladdr"
]
RISC_INSTRUCTIONS =
Modified: trunk/Source/bmalloc/ChangeLog (222624 => 222625)
--- trunk/Source/bmalloc/ChangeLog 2017-09-28 19:35:10 UTC (rev 222624)
+++ trunk/Source/bmalloc/ChangeLog 2017-09-28 19:50:05 UTC (rev 222625)
@@ -1,3 +1,15 @@
+2017-09-28 Filip Pizlo <fpi...@apple.com>
+
+ Enable gigacage on iOS
+ https://bugs.webkit.org/show_bug.cgi?id=177586
+
+ Reviewed by Michael Saboff.
+
+ This enables Gigacage on iOS using a much smaller cage size. It's not necessary for it to be so
+ small, but this is a good conservative starting point to start to exercise the code.
+
+ * bmalloc/Gigacage.h:
+
2017-09-26 Filip Pizlo <fpi...@apple.com>
Put g_gigacageBasePtr into its own page and make it read-only
Modified: trunk/Source/bmalloc/bmalloc/Gigacage.h (222624 => 222625)
--- trunk/Source/bmalloc/bmalloc/Gigacage.h 2017-09-28 19:35:10 UTC (rev 222624)
+++ trunk/Source/bmalloc/bmalloc/Gigacage.h 2017-09-28 19:50:05 UTC (rev 222625)
@@ -32,9 +32,17 @@
#include <cstddef>
#include <inttypes.h>
+#if BCPU(ARM64)
+// FIXME: This can probably be a lot bigger on iOS. I just haven't tried to make it bigger yet.
+// https://bugs.webkit.org/show_bug.cgi?id=177605
+#define PRIMITIVE_GIGACAGE_SIZE 0x40000000llu
+#define JSVALUE_GIGACAGE_SIZE 0x40000000llu
+#define STRING_GIGACAGE_SIZE 0x40000000llu
+#else
#define PRIMITIVE_GIGACAGE_SIZE 0x800000000llu
#define JSVALUE_GIGACAGE_SIZE 0x400000000llu
#define STRING_GIGACAGE_SIZE 0x400000000llu
+#endif
#define GIGACAGE_SIZE_TO_MASK(size) ((size) - 1)
@@ -42,9 +50,15 @@
#define JSVALUE_GIGACAGE_MASK GIGACAGE_SIZE_TO_MASK(JSVALUE_GIGACAGE_SIZE)
#define STRING_GIGACAGE_MASK GIGACAGE_SIZE_TO_MASK(STRING_GIGACAGE_SIZE)
+#if BCPU(ARM64)
+// FIXME: There is no good reason for ARM64 to be special.
+// https://bugs.webkit.org/show_bug.cgi?id=177605
+#define PRIMITIVE_GIGACAGE_RUNWAY 0
+#else
// FIXME: Consider making this 32GB, in case unsigned 32-bit indices find their way into indexed accesses.
// https://bugs.webkit.org/show_bug.cgi?id=175062
#define PRIMITIVE_GIGACAGE_RUNWAY (16llu * 1024 * 1024 * 1024)
+#endif
// FIXME: Reconsider this.
// https://bugs.webkit.org/show_bug.cgi?id=175921
@@ -51,13 +65,17 @@
#define JSVALUE_GIGACAGE_RUNWAY 0
#define STRING_GIGACAGE_RUNWAY 0
-#if BOS(DARWIN) && BCPU(X86_64)
+#if BOS(DARWIN) && (BCPU(ARM64) || BCPU(X86_64))
#define GIGACAGE_ENABLED 1
#else
#define GIGACAGE_ENABLED 0
#endif
-#define GIGACAGE_BASE_PTRS_SIZE 8192
+#if BCPU(ARM64)
+#define GIGACAGE_BASE_PTRS_SIZE 16384
+#else
+#define GIGACAGE_BASE_PTRS_SIZE 4096
+#endif
extern "C" BEXPORT char g_gigacageBasePtrs[GIGACAGE_BASE_PTRS_SIZE] __attribute__((aligned(GIGACAGE_BASE_PTRS_SIZE)));
