Title: [287465] trunk/Source
- Revision
- 287465
- Author
- commit-qu...@webkit.org
- Date
- 2021-12-28 01:06:36 -0800 (Tue, 28 Dec 2021)
Log Message
[RISCV64] Enable signal-based VM traps for CPU(RISCV64)
https://bugs.webkit.org/show_bug.cgi?id=234719
Patch by Zan Dobersek <zdober...@igalia.com> on 2021-12-28
Reviewed by Yusuke Suzuki.
Source/_javascript_Core:
Enable signal-based VM traps on RISCV64. On Linux, this depends on
generating a SIGSEGV or SIGBUS signal. The former can be generated
through a simple storage instruction that sources the address from
the zero register.
This storage instruction is generated on the desired location through
the RISCV64Assembler::replaceWithVMHalt() method.
* assembler/MacroAssemblerRISCV64.h:
(JSC::MacroAssemblerRISCV64::replaceWithVMHalt):
* assembler/RISCV64Assembler.h:
(JSC::RISCV64Assembler::replaceWithVMHalt):
Source/WTF:
* wtf/PlatformEnable.h: Define ENABLE_SIGNAL_BASED_VM_TRAPS for CPU(RISCV64).
Modified Paths
Diff
Modified: trunk/Source/_javascript_Core/ChangeLog (287464 => 287465)
--- trunk/Source/_javascript_Core/ChangeLog 2021-12-28 08:48:32 UTC (rev 287464)
+++ trunk/Source/_javascript_Core/ChangeLog 2021-12-28 09:06:36 UTC (rev 287465)
@@ -1,5 +1,25 @@
2021-12-28 Zan Dobersek <zdober...@igalia.com>
+ [RISCV64] Enable signal-based VM traps for CPU(RISCV64)
+ https://bugs.webkit.org/show_bug.cgi?id=234719
+
+ Reviewed by Yusuke Suzuki.
+
+ Enable signal-based VM traps on RISCV64. On Linux, this depends on
+ generating a SIGSEGV or SIGBUS signal. The former can be generated
+ through a simple storage instruction that sources the address from
+ the zero register.
+
+ This storage instruction is generated on the desired location through
+ the RISCV64Assembler::replaceWithVMHalt() method.
+
+ * assembler/MacroAssemblerRISCV64.h:
+ (JSC::MacroAssemblerRISCV64::replaceWithVMHalt):
+ * assembler/RISCV64Assembler.h:
+ (JSC::RISCV64Assembler::replaceWithVMHalt):
+
+2021-12-28 Zan Dobersek <zdober...@igalia.com>
+
[RISCV64] Define HAVE_MACHINE_CONTEXT, provide mcontext_t accessors for CPU(RISCV64)
https://bugs.webkit.org/show_bug.cgi?id=234718
Modified: trunk/Source/_javascript_Core/assembler/MacroAssemblerRISCV64.h (287464 => 287465)
--- trunk/Source/_javascript_Core/assembler/MacroAssemblerRISCV64.h 2021-12-28 08:48:32 UTC (rev 287464)
+++ trunk/Source/_javascript_Core/assembler/MacroAssemblerRISCV64.h 2021-12-28 09:06:36 UTC (rev 287465)
@@ -1568,7 +1568,10 @@
}
template<PtrTag tag>
- static void replaceWithVMHalt(CodeLocationLabel<tag>) { }
+ static void replaceWithVMHalt(CodeLocationLabel<tag> instructionStart)
+ {
+ Assembler::replaceWithVMHalt(instructionStart.dataLocation());
+ }
template<PtrTag startTag, PtrTag destTag>
static void replaceWithJump(CodeLocationLabel<startTag> instructionStart, CodeLocationLabel<destTag> destination)
Modified: trunk/Source/_javascript_Core/assembler/RISCV64Assembler.h (287464 => 287465)
--- trunk/Source/_javascript_Core/assembler/RISCV64Assembler.h 2021-12-28 08:48:32 UTC (rev 287464)
+++ trunk/Source/_javascript_Core/assembler/RISCV64Assembler.h 2021-12-28 09:06:36 UTC (rev 287465)
@@ -1647,6 +1647,13 @@
cacheFlush(location, sizeof(uint32_t) * 2);
}
+ static void replaceWithVMHalt(void* where)
+ {
+ uint32_t* location = reinterpret_cast<uint32_t*>(where);
+ location[0] = RISCV64Instructions::SD::construct(RISCV64Registers::zero, RISCV64Registers::zero, SImmediate::v<SImmediate, 0>());
+ cacheFlush(location, sizeof(uint32_t));
+ }
+
static void replaceWithJump(void* from, void* to)
{
uint32_t* location = reinterpret_cast<uint32_t*>(from);
Modified: trunk/Source/WTF/ChangeLog (287464 => 287465)
--- trunk/Source/WTF/ChangeLog 2021-12-28 08:48:32 UTC (rev 287464)
+++ trunk/Source/WTF/ChangeLog 2021-12-28 09:06:36 UTC (rev 287465)
@@ -1,5 +1,14 @@
2021-12-28 Zan Dobersek <zdober...@igalia.com>
+ [RISCV64] Enable signal-based VM traps for CPU(RISCV64)
+ https://bugs.webkit.org/show_bug.cgi?id=234719
+
+ Reviewed by Yusuke Suzuki.
+
+ * wtf/PlatformEnable.h: Define ENABLE_SIGNAL_BASED_VM_TRAPS for CPU(RISCV64).
+
+2021-12-28 Zan Dobersek <zdober...@igalia.com>
+
[RISCV64] Define HAVE_MACHINE_CONTEXT, provide mcontext_t accessors for CPU(RISCV64)
https://bugs.webkit.org/show_bug.cgi?id=234718
Modified: trunk/Source/WTF/wtf/PlatformEnable.h (287464 => 287465)
--- trunk/Source/WTF/wtf/PlatformEnable.h 2021-12-28 08:48:32 UTC (rev 287464)
+++ trunk/Source/WTF/wtf/PlatformEnable.h 2021-12-28 09:06:36 UTC (rev 287465)
@@ -788,7 +788,7 @@
#define ENABLE_EXCEPTION_SCOPE_VERIFICATION ASSERT_ENABLED
#endif
-#if ENABLE(DFG_JIT) && HAVE(MACHINE_CONTEXT) && (CPU(X86_64) || CPU(ARM64))
+#if ENABLE(DFG_JIT) && HAVE(MACHINE_CONTEXT) && (CPU(X86_64) || CPU(ARM64) || CPU(RISCV64))
#define ENABLE_SIGNAL_BASED_VM_TRAPS 1
#endif
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