flight 36775 xen-4.5-testing real [real]
http://www.chiark.greenend.org.uk/~xensrcts/logs/36775/
Regressions :-(
Tests which did not succeed and are blocking,
including tests which could not be run:
test-amd64-amd64-xl-qemuu-debianhvm-amd64 7 debian-hvm-install fail REGR. vs.
36511
Regressions
flight 36774 libvirt real [real]
http://www.chiark.greenend.org.uk/~xensrcts/logs/36774/
Failures :-/ but no regressions.
Tests which did not succeed, but are not blocking:
test-amd64-i386-libvirt-xsm 9 guest-start fail never pass
test-amd64-amd64-libvirt-xsm 9 guest-start
flight 36772 xen-unstable real [real]
http://www.chiark.greenend.org.uk/~xensrcts/logs/36772/
Regressions :-(
Tests which did not succeed and are blocking,
including tests which could not be run:
test-amd64-amd64-xl-credit2 12 guest-localmigratefail REGR. vs. 36514
test-amd64-amd64-xl
On Thu, Mar 26, 2015 at 04:32:45PM +0100, Roger Pau Monné wrote:
> El 26/03/15 a les 13.16, Bob Liu ha escrit:
> > There are several place using gnttab async unmap and wait for
> > completion, so move the common code to a function
> > gnttab_unmap_refs_async_wait_completion().
> >
> > Signed-off-b
On Fri, Mar 27, 2015 at 03:02:10PM -0700, Andy Lutomirski wrote:
> On Fri, Mar 27, 2015 at 2:56 PM, Ville Syrjälä wrote:
> > On Fri, Mar 27, 2015 at 08:57:59PM +0100, Luis R. Rodriguez wrote:
> >> On Fri, Mar 27, 2015 at 12:43:55PM -0700, Andy Lutomirski wrote:
> >> > On Fri, Mar 27, 2015 at 12:38
On Fri, Mar 27, 2015 at 11:56:55PM +0200, Ville Syrjälä wrote:
> On Fri, Mar 27, 2015 at 08:57:59PM +0100, Luis R. Rodriguez wrote:
> > On Fri, Mar 27, 2015 at 12:43:55PM -0700, Andy Lutomirski wrote:
> > > On Fri, Mar 27, 2015 at 12:38 PM, Luis R. Rodriguez
> > > wrote:
> > > > On Sat, Mar 21, 2
On Fri, Mar 27, 2015 at 02:40:17PM -0600, Toshi Kani wrote:
> On Fri, 2015-03-20 at 16:17 -0700, Luis R. Rodriguez wrote:
> :
> > @@ -734,6 +742,7 @@ void __init mtrr_bp_init(void)
> > }
> >
> > if (mtrr_if) {
> > + mtrr_enabled = true;
> > set_num_var_ranges();
> >
On Fri, Mar 27, 2015 at 04:10:03PM -0700, Andy Lutomirski wrote:
> On Fri, Mar 27, 2015 at 4:04 PM, Luis R. Rodriguez wrote:
> > On Fri, Mar 27, 2015 at 02:23:16PM -0700, Andy Lutomirski wrote:
> >> On Fri, Mar 27, 2015 at 1:30 PM, Luis R. Rodriguez wrote:
> >> > On Fri, Mar 27, 2015 at 12:58:02P
On Fri, Mar 27, 2015 at 02:21:34PM -0700, Andy Lutomirski wrote:
> On Fri, Mar 27, 2015 at 1:12 PM, Luis R. Rodriguez wrote:
> > On Fri, Mar 20, 2015 at 04:52:18PM -0700, Andy Lutomirski wrote:
> >> On Fri, Mar 20, 2015 at 4:17 PM, Luis R. Rodriguez
> >> wrote:
> >> > diff --git a/drivers/video/f
On Fri, Mar 27, 2015 at 4:04 PM, Luis R. Rodriguez wrote:
> On Fri, Mar 27, 2015 at 02:23:16PM -0700, Andy Lutomirski wrote:
>> On Fri, Mar 27, 2015 at 1:30 PM, Luis R. Rodriguez wrote:
>> > On Fri, Mar 27, 2015 at 12:58:02PM -0700, Andy Lutomirski wrote:
>> >> On Fri, Mar 27, 2015 at 12:53 PM, L
On Fri, Mar 27, 2015 at 02:23:16PM -0700, Andy Lutomirski wrote:
> On Fri, Mar 27, 2015 at 1:30 PM, Luis R. Rodriguez wrote:
> > On Fri, Mar 27, 2015 at 12:58:02PM -0700, Andy Lutomirski wrote:
> >> On Fri, Mar 27, 2015 at 12:53 PM, Luis R. Rodriguez
> >> wrote:
> >> > On Fri, Mar 20, 2015 at 04
flight 36769 qemu-upstream-4.4-testing real [real]
http://www.chiark.greenend.org.uk/~xensrcts/logs/36769/
Regressions :-(
Tests which did not succeed and are blocking,
including tests which could not be run:
test-amd64-amd64-xl-qemuu-winxpsp3 7 windows-install fail REGR. vs. 31663
Tests w
On Fri, Mar 27, 2015 at 3:52 PM, Ian Campbell
wrote:
> On Thu, 2015-03-26 at 23:05 +0100, Tamas K Lengyel wrote:
> > Add missing structure definition for iabt and update the trap handling
> > mechanism to only inject the exception if the mem_access checker
> > decides to do so.
> >
> > Signed-off
On Fri, Mar 27, 2015 at 2:56 PM, Ville Syrjälä wrote:
> On Fri, Mar 27, 2015 at 08:57:59PM +0100, Luis R. Rodriguez wrote:
>> On Fri, Mar 27, 2015 at 12:43:55PM -0700, Andy Lutomirski wrote:
>> > On Fri, Mar 27, 2015 at 12:38 PM, Luis R. Rodriguez
>> > wrote:
>> > > On Sat, Mar 21, 2015 at 11:15
On 27/03/15 02:35, Kai Huang wrote:
> Hi all,
>
> This patch series adds PML support to Xen. Please kindly help to review it.
Overall this looks like a very good series, and it is particularly
helpful given the level of commenting.
Which platforms is/will PML be available for?
~Andrew
_
On Fri, Mar 27, 2015 at 1:30 PM, Luis R. Rodriguez wrote:
> On Fri, Mar 27, 2015 at 12:58:02PM -0700, Andy Lutomirski wrote:
>> On Fri, Mar 27, 2015 at 12:53 PM, Luis R. Rodriguez wrote:
>> > On Fri, Mar 20, 2015 at 04:48:46PM -0700, Andy Lutomirski wrote:
>> >> On Fri, Mar 20, 2015 at 4:17 PM, L
On Fri, Mar 27, 2015 at 1:12 PM, Luis R. Rodriguez wrote:
> On Fri, Mar 20, 2015 at 04:52:18PM -0700, Andy Lutomirski wrote:
>> On Fri, Mar 20, 2015 at 4:17 PM, Luis R. Rodriguez
>> wrote:
>> > diff --git a/drivers/video/fbdev/aty/atyfb_base.c
>> > b/drivers/video/fbdev/aty/atyfb_base.c
>> > ind
On 27/03/15 20:41, Konrad Rzeszutek Wilk wrote:
> On Fri, Mar 27, 2015 at 08:04:44PM +, Andrew Cooper wrote:
>> On 27/03/15 19:42, Konrad Rzeszutek Wilk wrote:
>>> On Thu, Mar 26, 2015 at 09:07:05PM +, Andrew Cooper wrote:
On 20/03/15 17:03, Ian Campbell wrote:
> On Fri, 2015-03-20
On 27/03/15 02:35, Kai Huang wrote:
> It's possible domain has already been in log-dirty mode when creating vcpu, in
> which case we should enable PML for this vcpu if PML has been enabled for the
> domain.
>
> Signed-off-by: Kai Huang
> ---
> xen/arch/x86/hvm/vmx/vmx.c | 24 +
On 27/03/15 02:35, Kai Huang wrote:
> This patch adds help functions to enable/disable PML, and flush PML buffer for
> single vcpu and particular domain for further use.
>
> Signed-off-by: Kai Huang
> ---
> xen/arch/x86/hvm/vmx/vmcs.c| 190
> +
> xen/i
On Fri, 2015-03-20 at 16:17 -0700, Luis R. Rodriguez wrote:
:
> @@ -734,6 +742,7 @@ void __init mtrr_bp_init(void)
> }
>
> if (mtrr_if) {
> + mtrr_enabled = true;
> set_num_var_ranges();
> init_table();
> if (use_intel()) {
On 27/03/15 02:35, Kai Huang wrote:
> A new 4K page pointer is added to arch_vmx_struct as PML buffer for vcpu. And
> a
> new 'status' field is added to vmx_domain to indicate whether PML is enabled
> for
> the domain or not. The 'status' field also can be used for further similiar
> purpose.
>
>
On 27/03/15 02:35, Kai Huang wrote:
> The patch adds PML definition and feature detection. Note PML won't be
> detected
> if PML is disabled from boot parameter. PML is also disabled in
> construct_vmcs,
> as it will only be enabled when domain is switched to log dirty mode.
>
> Signed-off-by: Ka
On 27/03/15 02:35, Kai Huang wrote:
> A top level EPT parameter "ept=" and a sub boolean "pml_enable" are
> added to control PML. Other booleans can be further added for any other EPT
> related features.
>
> Signed-off-by: Kai Huang
Please patch docs/misc/xen-command-line.markdown as well. See t
On Fri, Mar 27, 2015 at 08:04:44PM +, Andrew Cooper wrote:
> On 27/03/15 19:42, Konrad Rzeszutek Wilk wrote:
> > On Thu, Mar 26, 2015 at 09:07:05PM +, Andrew Cooper wrote:
> >> On 20/03/15 17:03, Ian Campbell wrote:
> >>> On Fri, 2015-03-20 at 11:45 -0400, Konrad Rzeszutek Wilk wrote:
> >>>
On 27/03/15 02:35, Kai Huang wrote:
> PML requires A/D bit support so enable it for further use.
>
> Signed-off-by: Kai Huang
> ---
> xen/arch/x86/hvm/vmx/vmcs.c| 1 +
> xen/arch/x86/mm/p2m-ept.c | 8 +++-
> xen/include/asm-x86/hvm/vmx/vmcs.h | 4 +++-
> xen/include/asm-x86/h
On Sat, Mar 21, 2015 at 04:08:00PM +0900, Hyong-Youb Kim wrote:
> On Fri, Mar 20, 2015 at 04:18:11PM -0700, Luis R. Rodriguez wrote:
> > From: "Luis R. Rodriguez"
> >
> > This driver already uses ioremap_wc() on the same range
> > so when write-combining is available that will be used
> > instead
On Fri, Mar 27, 2015 at 12:58:02PM -0700, Andy Lutomirski wrote:
> On Fri, Mar 27, 2015 at 12:53 PM, Luis R. Rodriguez wrote:
> > On Fri, Mar 20, 2015 at 04:48:46PM -0700, Andy Lutomirski wrote:
> >> On Fri, Mar 20, 2015 at 4:17 PM, Luis R. Rodriguez
> >> wrote:
> >> > From: "Luis R. Rodriguez"
On 26/03/15 12:38, Chao Peng wrote:
> CAT introduces a mechanism for software to enable cache allocation based
> on application priority or Class of Service(COS). Each COS can be
> configured using capacity bitmasks(CBM) to represent cache capacity
> and indicate the degree of overlap and isolation
flight 36768 linux-3.10 real [real]
http://www.chiark.greenend.org.uk/~xensrcts/logs/36768/
Regressions :-(
Tests which did not succeed and are blocking,
including tests which could not be run:
test-amd64-amd64-xl-qemut-winxpsp3 7 windows-install fail REGR. vs. 26303
Tests which are failin
On Fri, Mar 20, 2015 at 04:52:18PM -0700, Andy Lutomirski wrote:
> On Fri, Mar 20, 2015 at 4:17 PM, Luis R. Rodriguez
> wrote:
> > diff --git a/drivers/video/fbdev/aty/atyfb_base.c
> > b/drivers/video/fbdev/aty/atyfb_base.c
> > index 8025624..8875e56 100644
> > --- a/drivers/video/fbdev/aty/atyfb
On 27/03/15 19:42, Konrad Rzeszutek Wilk wrote:
> On Thu, Mar 26, 2015 at 09:07:05PM +, Andrew Cooper wrote:
>> On 20/03/15 17:03, Ian Campbell wrote:
>>> On Fri, 2015-03-20 at 11:45 -0400, Konrad Rzeszutek Wilk wrote:
From 45bd7cd377b0b8364757cc2bc0bd8d6a13523a97 Mon Sep 17 00:00:00 2001
On Fri, Mar 27, 2015 at 12:53 PM, Luis R. Rodriguez wrote:
> On Fri, Mar 20, 2015 at 04:48:46PM -0700, Andy Lutomirski wrote:
>> On Fri, Mar 20, 2015 at 4:17 PM, Luis R. Rodriguez
>> wrote:
>> > From: "Luis R. Rodriguez"
>> >
>> > Ideally on systems using PAT we can expect a swift
>> > transitio
On Fri, Mar 27, 2015 at 12:43:55PM -0700, Andy Lutomirski wrote:
> On Fri, Mar 27, 2015 at 12:38 PM, Luis R. Rodriguez wrote:
> > On Sat, Mar 21, 2015 at 11:15:14AM +0200, Ville Syrjälä wrote:
> >> On Fri, Mar 20, 2015 at 04:17:59PM -0700, Luis R. Rodriguez wrote:
> >> > diff --git a/drivers/video
On Fri, Mar 20, 2015 at 04:48:46PM -0700, Andy Lutomirski wrote:
> On Fri, Mar 20, 2015 at 4:17 PM, Luis R. Rodriguez
> wrote:
> > From: "Luis R. Rodriguez"
> >
> > Ideally on systems using PAT we can expect a swift
> > transition away from MTRR. There can be a few exceptions
> > to this, one is
On Fri, Mar 27, 2015 at 12:38 PM, Luis R. Rodriguez wrote:
> On Sat, Mar 21, 2015 at 11:15:14AM +0200, Ville Syrjälä wrote:
>> On Fri, Mar 20, 2015 at 04:17:59PM -0700, Luis R. Rodriguez wrote:
>> > diff --git a/drivers/video/fbdev/aty/atyfb_base.c
>> > b/drivers/video/fbdev/aty/atyfb_base.c
>> >
On Thu, Mar 26, 2015 at 09:07:05PM +, Andrew Cooper wrote:
> On 20/03/15 17:03, Ian Campbell wrote:
> >On Fri, 2015-03-20 at 11:45 -0400, Konrad Rzeszutek Wilk wrote:
> >> From 45bd7cd377b0b8364757cc2bc0bd8d6a13523a97 Mon Sep 17 00:00:00 2001
> >>From: Konrad Rzeszutek Wilk
> >>Date: Fri, 13 M
On Fri, Mar 27, 2015 at 10:37:04AM +0200, Ville Syrjälä wrote:
> On Sat, Mar 21, 2015 at 11:15:14AM +0200, Ville Syrjälä wrote:
> > On Fri, Mar 20, 2015 at 04:17:59PM -0700, Luis R. Rodriguez wrote:
> > > diff --git a/drivers/video/fbdev/aty/atyfb_base.c
> > > b/drivers/video/fbdev/aty/atyfb_base.
On Sat, Mar 21, 2015 at 11:15:14AM +0200, Ville Syrjälä wrote:
> On Fri, Mar 20, 2015 at 04:17:59PM -0700, Luis R. Rodriguez wrote:
> > diff --git a/drivers/video/fbdev/aty/atyfb_base.c
> > b/drivers/video/fbdev/aty/atyfb_base.c
> > index 8025624..8875e56 100644
> > --- a/drivers/video/fbdev/aty/a
On Mon, 2015-03-23 at 12:20 -0500, Bjorn Helgaas wrote:
:
> pci_iomap_range() already makes a cacheable mapping if
> IORESOURCE_CACHEABLE; I'm guessing that you would like it to
> automatically use WC if the BAR if IORESOURCE_PREFETCH, e.g.,
>
> if (flags & IORESOURCE_CACHEABLE)
> return io
On 27/03/2015 18:05, Jaggi, Manish wrote:
From: Julien Grall
Sent: Friday, March 27, 2015 7:11 PM
To: Jaggi, Manish; Xen Devel; prasun.kap...@cavium.com; Kumar, Vijaya; Ian
Campbell; Stefano Stabellini
Subject: Re: [PATCH v1 3/3] xen/arm: smmu: Renaming struct iommu_domain *domain
to, struct
flight 36771 rumpuserxen real [real]
http://www.chiark.greenend.org.uk/~xensrcts/logs/36771/
Regressions :-(
Tests which did not succeed and are blocking,
including tests which could not be run:
build-amd64-rumpuserxen 5 rumpuserxen-build fail REGR. vs. 33866
build-i386-rumpuserxe
to appease the Missing Break checker.
Signed-off-by: Andrew Cooper
Coverity-id: 1291938
CC: Keir Fraser
CC: Jan Beulich
CC: Xen Coverity Team
---
xen/arch/x86/acpi/cpu_idle.c |1 +
1 file changed, 1 insertion(+)
diff --git a/xen/arch/x86/acpi/cpu_idle.c b/xen/arch/x86/acpi/cpu_idle.c
ind
On Fri, Mar 27, 2015 at 06:44:52PM +, Andrew Cooper wrote:
> Introduced by c/s 1781f00e
>
> Signed-off-by: Andrew Cooper
> Coverity-IDs: 1291939 (stray semicolon), 1291941 (structually dead code)
> CC: Konrad Rzeszutek Wilk
Reviewed-by: Konrad Rzeszutek Wilk
> CC: Ian Campbell
> CC: Ian J
Introduced by c/s 1781f00e
Signed-off-by: Andrew Cooper
Coverity-IDs: 1291939 (stray semicolon), 1291941 (structually dead code)
CC: Konrad Rzeszutek Wilk
CC: Ian Campbell
CC: Ian Jackson
CC: Wei Liu
CC: Xen Coverity Team
---
tools/misc/xen-mfndump.c |2 +-
1 file changed, 1 insertion(+
On Wed, Mar 25, 2015 at 04:07:43PM -0400, Konrad Rzeszutek Wilk wrote:
> On Fri, Mar 20, 2015 at 04:17:55PM -0700, Luis R. Rodriguez wrote:
> > From: "Luis R. Rodriguez"
> >
> > This allows drivers to take advantage of write-combining
> > when possible. Ideally we'd have pci_read_bases() just
> >
On 27 March 2015 at 09:48, Jan Beulich wrote:
> >>> On 26.03.15 at 20:37, wrote:
> > Without Xen, first the disk is deliberately ignored:
> >
> > [3.728055] ata_piix :00:07.1: Hyper-V Virtual Machine detected,
> ATA
> > device ignore set
> >
> > And later picked up by hv_storevsc:
> >
>
Konrad Rzeszutek Wilk wrote:
> On Wed, Mar 25, 2015 at 02:08:33PM -0600, Jim Fehlig wrote:
>
>> This small series of patches fixes some issues wrt domain destroy in
>> the libxl driver. The primary motivation for this work is to
>> prevent locking the virDomainObj during long running destroy op
On 26/03/15 12:38, Chao Peng wrote:
> Detect Intel Cache Allocation Technology(CAT) feature and store the
> cpuid information for later use. Currently only L3 cache allocation is
> supported. The L3 CAT features may vary among sockets so per-socket
> feature information is stored. The initializatio
On Wed, Mar 25, 2015 at 02:08:33PM -0600, Jim Fehlig wrote:
> This small series of patches fixes some issues wrt domain destroy in
> the libxl driver. The primary motivation for this work is to
> prevent locking the virDomainObj during long running destroy operations
> on large memory domains.
>
On 26/03/15 12:38, Chao Peng wrote:
> Switching RMID from previous vcpu to next vcpu only needs to write
> MSR_IA32_PSR_ASSOC once. Write it with the value of next vcpu is enough,
> no need to write '0' first. Idle domain has RMID set to 0 and because MSR
> is already updated lazily, so just switch
On Fri, Mar 27, 2015 at 09:32:10AM +0100, Roger Pau Monné wrote:
> El 27/03/15 a les 0.33, Luis R. Rodriguez ha escrit:
> > From: "Luis R. Rodriguez"
> >
> > Commit 586ab6a by Roger disabled the main MTRR CPU feature
> > on the cpuid when on pvh in order to avoid having MTRR code
> > run on the O
From: Julien Grall
Sent: Friday, March 27, 2015 7:11 PM
To: Jaggi, Manish; Xen Devel; prasun.kap...@cavium.com; Kumar, Vijaya; Ian
Campbell; Stefano Stabellini
Subject: Re: [PATCH v1 3/3] xen/arm: smmu: Renaming struct iommu_domain *domain
to, struct iommu_domain *iommu_domain
On 27/03/15 13:26
From: Julien Grall
Sent: Friday, March 27, 2015 7:05 PM
To: Jaggi, Manish; Xen Devel; Stefano Stabellini; Ian Campbell;
prasun.kap...@cavium.com; Kumar, Vijaya
Subject: Re: [PATCH v1 1/3] xen/arm: smmu: Rename arm_smmu_xen_device with,
device_iommu_info
On 27/03
Regards,
Manish Jaggi
From: Julien Grall
Sent: Friday, March 27, 2015 7:06 PM
To: Jaggi, Manish; Xen Devel; prasun.kap...@cavium.com; Kumar, Vijaya; Ian
Campbell; Stefano Stabellini
Subject: Re: [PATCH v1 2/3] xen/arm: smmu: Renaming arm_smmu_xen_domain
Hello Vijay,
On 19/03/15 14:38, vijay.kil...@gmail.com wrote:
> +/*
> + * Map the 64K ITS translation space in guest.
> + * This is required purely for device smmu writes.
> +*/
Could this be avoid if the SMMU is not present?
> +
> +static int vgic_map_translation_space(uint32_t nr_its, struct d
On Fri, 2015-03-27 at 17:31 +0100, Atom2 wrote:
> Am 27.03.15 um 10:28 schrieb Ian Campbell:
> > Unfortunately this has unexpectedly made things worse. See:
> > http://www.chiark.greenend.org.uk/~xensrcts/logs/36757/
> >
> > The issue is that readlink -f returns the full absolute path, so given
> >
On Fri, 2015-03-27 at 16:36 +, Julien Grall wrote:
> Hi Ian,
>
> On 27/03/15 14:33, Ian Campbell wrote:
> > We set HCR_EL2.TSW but only (sort of) handle 32-bit access to DCCISW
> > but not the other two registers, nor any 64-bit access. Add handlers
> > for all of these.
>
> We don't set HCR_
Hello Vijay,
On 19/03/15 14:38, vijay.kil...@gmail.com wrote:
> diff --git a/xen/arch/arm/gic-v3.c b/xen/arch/arm/gic-v3.c
> index 2b406e6..1b3ecd7 100644
> --- a/xen/arch/arm/gic-v3.c
> +++ b/xen/arch/arm/gic-v3.c
> @@ -40,6 +40,7 @@
> #include
> #include
> #include
> +#include
> #include
Hi Ian,
On 27/03/15 14:33, Ian Campbell wrote:
> Using !usr_mode(regs) only catches arm32 usr mode and not arm64 user
> mode, switch to psr_mode_is_user instead.
>
> Signed-off-by: Ian Campbell
It might be a good backport
Reviewed-by: Julien Grall
Regards,
--
Julien Grall
Hi Ian,
On 27/03/15 14:33, Ian Campbell wrote:
> Previously we implemented all registers as RAZ/WI even if they
> shouldn't be accessible to userspace.
>
> It is not entirely clear whether attempts to access *_EL1 registers
> from EL0 will trap to EL1 or EL2, be conservative and treat as an
> und
Hi Ian,
On 27/03/15 14:33, Ian Campbell wrote:
> Previously userspace access to PM* would have been incorrectly (but
> benignly) implemented as RAZ/WI when running on a 32-bit kernel and
> would cause a hypervisor exception (host crash) when running a 64-bit
> kernel (this was already solved via t
Hi Ian,
On 27/03/15 14:33, Ian Campbell wrote:
> We set HCR_EL2.TSW but only (sort of) handle 32-bit access to DCCISW
> but not the other two registers, nor any 64-bit access. Add handlers
> for all of these.
We don't set HCR_EL2.TSW so DCCISW is not trapped.
> diff --git a/xen/include/public/ar
Am 27.03.15 um 10:28 schrieb Ian Campbell:
Unfortunately this has unexpectedly made things worse. See:
http://www.chiark.greenend.org.uk/~xensrcts/logs/36757/
The issue is that readlink -f returns the full absolute path, so given
$ ls /boot/xen*
xen -> xen-X.Y
xen-X.Y
Then:
$
Hi Ian,
On 27/03/15 14:33, Ian Campbell wrote:
> They are trapped only with HCR_EL2.TID2 which we don't set, and in any
> case we handled only for 32-bit.
>
> One day we may want to trap and emulate these, but for now don't
> bother with the dead code.
>
> Signed-off-by: Ian Campbell
Reviewed-
Hi Ian,
On 27/03/15 14:33, Ian Campbell wrote:
> All OSes we have run on top of Xen use CNTP_TVAL_EL0 but for
> completeness we really should handle CVAL too.
>
> In vtimer_emulate_cp64 pull the propagation of the 64-bit result into
> two 32-bit registers out of the switch to avoid duplicating fo
Hi Ian,
On 27/03/15 14:33, Ian Campbell wrote:
> Previously 32-bit userspace on 32-bit kernel and 64-bit userspace on
> 64-bit kernel could access these registers irrespective of whether the
> kernel had configured them to be allowed to. To fix this:
>
> - Userspace access to CNTP_CTL_EL0 and CN
On Thu, 2015-03-26 at 23:05 +0100, Tamas K Lengyel wrote:
> Add missing structure definition for iabt and update the trap handling
> mechanism to only inject the exception if the mem_access checker
> decides to do so.
>
> Signed-off-by: Tamas K Lengyel
> Acked-by: Ian Campbell
> Reviewed-by: Ju
Hello Vijay,
On 19/03/15 14:38, vijay.kil...@gmail.com wrote:
> From: Vijaya Kumar K
>
> With this patch add emulation of GICR registers for LPIs.
> Also add LPI property table emulation.
>
> Domain's LPI property table is unmapped during domain init
> on LPIPROPBASE update and trapped on LPI p
flight 36767 linux-3.16 real [real]
http://www.chiark.greenend.org.uk/~xensrcts/logs/36767/
Regressions :-(
Tests which did not succeed and are blocking,
including tests which could not be run:
test-amd64-amd64-xl-credit2 15 guest-localmigrate/x10fail REGR. vs. 34167
test-amd64-i386-pair
On Fri, Mar 27, 2015 at 03:06:43PM +, Jan Beulich wrote:
> >>> On 27.03.15 at 15:57, wrote:
> > On Fri, Mar 27, 2015 at 02:34:19PM +, Jan Beulich wrote:
> >> >>> On 27.03.15 at 15:26, wrote:
> >> > On Fri, Mar 27, 2015 at 01:36:32PM +, Jan Beulich wrote:
> >> >> >>> On 27.03.15 at 14:
>>> On 27.03.15 at 15:57, wrote:
> On Fri, Mar 27, 2015 at 02:34:19PM +, Jan Beulich wrote:
>> >>> On 27.03.15 at 15:26, wrote:
>> > On Fri, Mar 27, 2015 at 01:36:32PM +, Jan Beulich wrote:
>> >> >>> On 27.03.15 at 14:06, wrote:
>> >> > On Tue, Mar 17, 2015 at 10:32:01AM +, Jan Beuli
On Fri, Mar 27, 2015 at 02:34:19PM +, Jan Beulich wrote:
> >>> On 27.03.15 at 15:26, wrote:
> > On Fri, Mar 27, 2015 at 01:36:32PM +, Jan Beulich wrote:
> >> >>> On 27.03.15 at 14:06, wrote:
> >> > On Tue, Mar 17, 2015 at 10:32:01AM +, Jan Beulich wrote:
> >> >> >>> On 30.01.15 at 18:
On Tue, 2015-03-24 at 11:45 +, Wei Liu wrote:
> Please set host property 'UBootSetFlaskAddrR' to 0x120.
For the new boards (both cubietruck and arndale) I think 0x4120 is
the correct choice.
That's 2M after xen_addr_r (as 0x120 is on Marilith) and doesn't
clash with anything.
I'v
On Fri, Mar 27, 2015 at 01:06:48AM +, Wu, Feng wrote:
>
>
> > -Original Message-
> > From: Konrad Rzeszutek Wilk [mailto:konrad.w...@oracle.com]
> > Sent: Friday, March 27, 2015 2:51 AM
> > To: Wu, Feng
> > Cc: xen-devel@lists.xen.org; Zhang, Yang Z; Tian, Kevin; k...@xen.org;
> > jbe
In the hopes of making any future errors along the lines of XSA-123
into clean crashes instead of memory corruption bugs.
Signed-off-by: Tim Deegan
Reviewed-by: Andrew Cooper
CC: Keir Fraser
CC: Jan Beulich
---
v3: drop unhelpful unnamed struct (Jan Beulich / gcc)
v2: tweak poison values (Andr
We set HCR_EL2.TSW but only (sort of) handle 32-bit access to DCCISW
but not the other two registers, nor any 64-bit access. Add handlers
for all of these.
The existing handling of DCCISW was to simply propagate the action to
the host level. This can't really work on an SMP system (due to
speculat
Fix a coding style issue while in the area.
Signed-off-by: Ian Campbell
Reviewed-by: Julien Grall
---
xen/arch/arm/traps.c |8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/xen/arch/arm/traps.c b/xen/arch/arm/traps.c
index cc34a0a..c5ffcc5 100644
--- a/xen/arch/arm/
Previously we implemented all registers as RAZ/WI even if they
shouldn't be accessible to userspace.
It is not entirely clear whether attempts to access *_EL1 registers
from EL0 will trap to EL1 or EL2, be conservative and treat as an
undef injection.
PMUSERENR_EL0 and MDCCSR_EL0 are R/O to EL0.
Accesses to these from 32-bit userspace would cause a hypervisor
exception (host crash) when running a 64-bit kernel, which is worked
around by the fix to XSA-102. On 32-bit kernels they would be
implemented as RAZ/WI which is incorrect but harmless.
Update as follows:
- DBGDSCRINT should be R/O.
All OSes we have run on top of Xen use CNTP_TVAL_EL0 but for
completeness we really should handle CVAL too.
In vtimer_emulate_cp64 pull the propagation of the 64-bit result into
two 32-bit registers out of the switch to avoid duplicating for every
register. We also need to initialise x now since p
By adding GUEST_BUG_ON locally to traps.c.
Signed-off-by: Ian Campbell
Reviewed-by: Julien Grall
---
v4: This is now only used for HSR decode and no in the individual do_*
which instead inject undef.
v3: New patch
---
xen/arch/arm/traps.c | 44 ++--
This embodies the logic on arm64 that userspace can be either 32-bit
or 64-bit. It will be used in other places shortly.
Note that the logic differs slightly because the original (in
inject_abt64_exception) knew that the kernel was 64-bit and could
therefore assume that any 32-bit mode was userspa
p15,0,c9,c13,1 is PMXEVTYPER not PMXEVCNTR.
p15,0,c9,c13,2 is PMXEVCNTR not PMXEVCNR.
Signed-off-by: Ian Campbell
Reviewed-by: Julien Grall
---
xen/arch/arm/traps.c |2 +-
xen/include/asm-arm/cpregs.h |4 ++--
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/xen/ar
Using !usr_mode(regs) only catches arm32 usr mode and not arm64 user
mode, switch to psr_mode_is_user instead.
Signed-off-by: Ian Campbell
---
v4: New patch
---
xen/arch/arm/traps.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/xen/arch/arm/traps.c b/xen/arch/arm/traps.c
Previously userspace access to PM* would have been incorrectly (but
benignly) implemented as RAZ/WI when running on a 32-bit kernel and
would cause a hypervisor exception (host crash) when running a 64-bit
kernel (this was already solved via the fix to XSA-102).
PMINTENSET, PMINTENCLR are EL1 only
>>> On 27.03.15 at 15:26, wrote:
> On Fri, Mar 27, 2015 at 01:36:32PM +, Jan Beulich wrote:
>> >>> On 27.03.15 at 14:06, wrote:
>> > On Tue, Mar 17, 2015 at 10:32:01AM +, Jan Beulich wrote:
>> >> >>> On 30.01.15 at 18:54, wrote:
>> >> > +/* Skip Multiboot2 information fixed part
They are trapped only with HCR_EL2.TID2 which we don't set, and in any
case we handled only for 32-bit.
One day we may want to trap and emulate these, but for now don't
bother with the dead code.
Signed-off-by: Ian Campbell
---
v4: New patch
---
xen/arch/arm/traps.c | 18 --
1
Rather than using the v8 register names and the v7 bit names, which
makes things needlessly difficult when reading.
Signed-off-by: Ian Campbell
Reviewed-by: Julien Grall
---
v3: New patch.
---
xen/arch/arm/time.c |2 +-
xen/include/asm-arm/processor.h |4 ++--
2 files change
This removes the unconditional #undef injected in response to such
traps which was added by the fixes to CVE-2014-5147 / XSA-102 in
c0020e099702 "xen: arm: Handle traps from 32-bit userspace on 64-bit
kernel as undef", we now handle such traps correctly.
Signed-off-by: Ian Campbell
Reviewed-by: J
XSA-102/CVE-2014-5147[0] concerned a crash when trapping from 32-bit
userspace in a 64-bit guest. Part of that security patch was c0020e09970
"xen: arm: Handle traps from 32-bit userspace on 64-bit kernel as undef
fix" which turned the exploitable crash into a #undef to the guest (so
as to kill the
CP14 dbg and general CP register access are both handled with
unconditional injection of #undef from their respective handlers, so
allow these even from 32-bit userspace on a 64-bit kernel.
SMC32 and HVC32 should only come from a guest in AArch32 mode and
SMC64 and HVC64 should only come from a gu
Previously 32-bit userspace on 32-bit kernel and 64-bit userspace on
64-bit kernel could access these registers irrespective of whether the
kernel had configured them to be allowed to. To fix this:
- Userspace access to CNTP_CTL_EL0 and CNTP_TVAL_EL0 should be gated
on CNTKCTL_EL1.EL0PTEN.
-
>>> On 26.03.15 at 13:40, wrote:
> @@ -1447,14 +1452,15 @@ x86_emulate(
> unsigned int op_bytes, def_op_bytes, ad_bytes, def_ad_bytes;
> bool_t lock_prefix = 0;
> int override_seg = -1, rc = X86EMUL_OKAY;
> -struct operand src, dst;
> +struct operand src = { .reg = REG_POISO
On Fri, Mar 27, 2015 at 01:35:11PM +, Jan Beulich wrote:
> >>> On 27.03.15 at 13:57, wrote:
> > On Mon, Mar 02, 2015 at 05:23:49PM +, Jan Beulich wrote:
> >> >>> On 30.01.15 at 18:54, wrote:
> >> > +{
> >> > +void *ptr;
> >> > +
> >> > +/*
> >> > + * Init __malloc_free on runt
On Fri, Mar 27, 2015 at 01:36:32PM +, Jan Beulich wrote:
> >>> On 27.03.15 at 14:06, wrote:
> > On Tue, Mar 17, 2015 at 10:32:01AM +, Jan Beulich wrote:
> >> >>> On 30.01.15 at 18:54, wrote:
> >> > +/* Skip Multiboot2 information fixed part */
> >> > +lea MB2_fixed_siz
On Fri, Mar 27, 2015 at 02:19:44PM +, Jan Beulich wrote:
> >>> On 27.03.15 at 15:09, wrote:
> > On Fri, Mar 27, 2015 at 02:04:22PM +, Jan Beulich wrote:
> >> >>> On 27.03.15 at 14:53, wrote:
> >> > On 27/03/15 13:43, Jan Beulich wrote:
> >> > On 27.03.15 at 14:32, wrote:
> >> >>> On
>>> On 27.03.15 at 15:09, wrote:
> On Fri, Mar 27, 2015 at 02:04:22PM +, Jan Beulich wrote:
>> >>> On 27.03.15 at 14:53, wrote:
>> > On 27/03/15 13:43, Jan Beulich wrote:
>> > On 27.03.15 at 14:32, wrote:
>> >>> On Fri, Feb 20, 2015 at 04:17:35PM +, Jan Beulich wrote:
>> >>> On 3
On Fri, Mar 27, 2015 at 10:52:07AM +, Ian Campbell wrote:
> On Thu, 2015-03-26 at 21:07 +, Andrew Cooper wrote:
> > On 20/03/15 17:03, Ian Campbell wrote:
> > > On Fri, 2015-03-20 at 11:45 -0400, Konrad Rzeszutek Wilk wrote:
> > >> From 45bd7cd377b0b8364757cc2bc0bd8d6a13523a97 Mon Sep 17 0
On Fri, Mar 27, 2015 at 09:52:49AM +0100, Roger Pau Monné wrote:
> El 27/03/15 a les 14.15, Tao Chen ha escrit:
> > The blkback name is like blkback.domid.xvd[a-z], if domid has four digits
> > (means larger than 1000), then the backmost xvd wouldn't be fully shown.
> >
> > Define a BLKBACK_NAME_L
1 - 100 of 184 matches
Mail list logo
