Hi Julien,
On 24/04/2015 20:57, Julien Grall wrote
> On 23/04/2016 18:58, Wei Wang wrote:
> > diff --git a/xen/include/acpi/cpufreq/processor_perf.h
> > b/xen/include/acpi/cpufreq/processor_perf.h
> > index d8a1ba6..ebff11d 100644
> > --- a/xen/include/acpi/cpufreq/processor_perf.h
> > +++ b/xen/i
Hi Suravee,
Thanks for adding support of GICv2m.
I left Linaro at the beginning of the month. Can you use my citrix email
(julien.gr...@citrix.com)?
On 23/04/2015 09:51, Suravee Suthikulpanit wrote:
This patch series introduce GICv2m supports in Xen Dom0.
It looks like that the approach ta
Hi Pranav,
On 24/04/2015 15:46, Pranavkumar Sawargaonkar wrote:
In old X-Gene Storm firmware and DT, secure mode addresses have been
mentioned in GICv2 node. In this case maintenance interrupt is used
instead of EOI HW method.
This patch checks the GIC Distributor Base Address to enable EOI qui
Hi Ian,
On 17/04/2015 19:01, Ian Campbell wrote:
Add explicit handler for 64-bit CP14 accesses, with more relevant
debug message (as per other handlers) and to provide a place for a
comment.
Signed-off-by: Ian Campbell
Reviewed-by: Julien Grall
Regards,
--
Julien Grall
__
Hi Ian,
On 17/04/2015 19:01, Ian Campbell wrote:
Signed-off-by: Ian Campbell
---
v2: s/Tx/T15/
---
xen/arch/arm/traps.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/xen/arch/arm/traps.c b/xen/arch/arm/traps.c
index a2bae51..86b5655 100644
--- a/xen/arch/arm/traps.c
+++ b
Hi Ian,
On 17/04/2015 19:01, Ian Campbell wrote:
Removes a load of boiler plate.
Signed-off-by: Ian Campbell
Reviewed-by: Julien Grall
Regards,
--
Julien Grall
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Hi Ian,
On 17/04/2015 19:01, Ian Campbell wrote:
DBGDRAR and DBGDSAR are actually two cp or sys registers each, one
32-bit and one 64-bit. The cpregs #define is suffixed "64" and
annotations are added to both handlers.
MDRAR_EL1 (arm64 version of DBGDRAR) wasn't handled, so add that here.
Sign
Hi Ian,
On 17/04/2015 19:01, Ian Campbell wrote:
Reduces the use of goto in the trap handlers to none.
Some explicitly 32-bit types become register_t here, but that's OK, on
32-bit they are 32-bit already and on 64-bit it is fine/harmless to
set the larger register, a 32-bit guest won't see the
Hi Ian,
On 17/04/2015 19:01, Ian Campbell wrote:
Gather the affected handlers in a single place per trap type.
Add some HSR_SYSREG and AArch32 defines for those registers (because
I'd already typed them in when I realised I didn't need them).
Signed-off-by: Ian Campbell
Reviewed-by: Julien G
Hi Ian,
On 17/04/2015 19:01, Ian Campbell wrote:
Also expand on the comment when writing CPTR_EL2 to mention that most
of the bits we are setting are RES1 on arm64 anyway.
Signed-off-by: Ian Campbell
Reviewed-by: Julien Grall
Regards,
--
Julien Grall
_
Hi Ian,
On 17/04/2015 19:01, Ian Campbell wrote:
While annotating ACTLR I noticed that we don't appear to handle the
64-bit version of this trap. Do so and annotate everything.
Signed-off-by: Ian Campbell
Reviewed-by: Julien Grall
Regards,
--
Julien Grall
Hi Ian,
Subject: s/HSR_EL2/HCR_EL2/
On 17/04/2015 19:01, Ian Campbell wrote:
Reference the bit which enables the trap and the section/page which
describes what that bit enables.
These ones are pretty trivial, included for completeness.
Signed-off-by: Ian Campbell
Other than the typo in the
Hi Wei,
On 23/04/2016 18:58, Wei Wang wrote:
diff --git a/xen/include/acpi/cpufreq/processor_perf.h
b/xen/include/acpi/cpufreq/processor_perf.h
index d8a1ba6..ebff11d 100644
--- a/xen/include/acpi/cpufreq/processor_perf.h
+++ b/xen/include/acpi/cpufreq/processor_perf.h
@@ -7,6 +7,7 @@
#defin
Hi Ian,
On 17/04/2015 19:01, Ian Campbell wrote:
Gather the affected handlers in a single place per trap type.
Signed-off-by: Ian Campbell
Reviewed-by: Julien Grall
Regards,
--
Julien Grall
___
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http
Hi Ian,
On 17/04/2015 19:01, Ian Campbell wrote:
Signed-off-by: Ian Campbell
---
v2: Move last paramter of a handle_ro_raz call to next patch where it
belongs.
---
xen/arch/arm/traps.c | 52 --
1 file changed, 33 insertions(+), 19 deleti
Hi Jan,
On 21/04/2015 20:13, Jan Beulich wrote:
For this specific one - is there a reasonable use case? Other than
for host PFN, we have control over guest ones, and I'm not sure
managing a guest with GPFNs extending past 4 billion can be
expected to work if only this one hypercall got fixed. IO
On Fri, Apr 24, 2015 at 10:33 PM, Jan Beulich wrote:
On 24.04.15 at 10:19, wrote:
>> --- a/xen/arch/x86/hvm/vmx/vmcs.c
>> +++ b/xen/arch/x86/hvm/vmx/vmcs.c
>> @@ -64,6 +64,36 @@ integer_param("ple_gap", ple_gap);
>> static unsigned int __read_mostly ple_window = 4096;
>> integer_param("ple
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