On 2017.09.21 at 14:21 -0700, Thomas Garnier wrote:
> On Thu, Sep 21, 2017 at 9:10 AM, Ard Biesheuvel
> wrote:
> >
> > On 21 September 2017 at 08:59, Ingo Molnar wrote:
> > >
> > > ( Sorry about the delay in answering this. I could blame the delay on
Hi Jan,
On 18 September 2017 at 16:15, Jan Beulich wrote:
On 18.09.17 at 12:31, wrote:
>> --- a/xen/include/public/domctl.h
>> +++ b/xen/include/public/domctl.h
>> @@ -36,6 +36,7 @@
>> #include "grant_table.h"
>> #include "hvm/save.h"
>>
flight 113680 linux-4.9 real [real]
http://logs.test-lab.xenproject.org/osstest/logs/113680/
Regressions :-(
Tests which did not succeed and are blocking,
including tests which could not be run:
build-armhf-libvirt broken in 113640
build-armhf-pvops
flight 113696 ovmf real [real]
http://logs.test-lab.xenproject.org/osstest/logs/113696/
Regressions :-(
Tests which did not succeed and are blocking,
including tests which could not be run:
build-amd64-xsm 6 xen-buildfail REGR. vs. 113647
build-i386-xsm
Commit 0ade5e causes a bug that the psr features presented in cmdline
cannot be correctly enumerated.
1. If there is only 'psr=', then CMT is enumerated which is not right.
2. If cmdline is 'psr=cmt,cat,cdp,mba', only the last feature is enumerated.
This patch fixes the issues.
Signed-off-by: Yi
On Tue, 19 Sep 2017, Rajiv Ranganath wrote:
> Hi Stefano,
>
> I've made the following changes based on v1 series feedback.
>
> Kindly please review.
I think this series is a good start, I committed it. However we have
hard-coded versions (such as "4.9.0") a bit everywhere, which makes it a
pain
On Thu, Sep 21, 2017 at 1:27 PM, Sander Eikelenboom
wrote:
>
> On Thu, September 21, 2017, 10:39:52 AM, Roger Pau Monné wrote:
>
>> On Wed, Sep 20, 2017 at 03:50:35PM -0400, Jérôme Oufella wrote:
>>>
>>> I'm using PCI pass-through to map a PCIe (intel i210) controller into
flight 113666 linux-linus real [real]
http://logs.test-lab.xenproject.org/osstest/logs/113666/
Failures :-/ but no regressions.
Tests which did not succeed, but are not blocking:
test-amd64-amd64-xl-qemut-win7-amd64 18 guest-start/win.repeat fail blocked in
113629
This run is configured for baseline tests only.
flight 72136 qemu-mainline real [real]
http://osstest.xs.citrite.net/~osstest/testlogs/logs/72136/
Regressions :-(
Tests which did not succeed and are blocking,
including tests which could not be run:
test-amd64-i386-xl-qemuu-win7-amd64 16
On Tue, 19 Sep 2017, Rajiv Ranganath wrote:
> From: Rajiv M Ranganath
>
> Signed-off-by: Rajiv Ranganath
Acked-by: Stefano Stabellini
> ---
> build/fedora/xen-4.9.0-runit/setup.sh | 18
flight 113668 qemu-upstream-unstable real [real]
http://logs.test-lab.xenproject.org/osstest/logs/113668/
Regressions :-(
Tests which did not succeed and are blocking,
including tests which could not be run:
test-amd64-i386-xl-qemuu-win7-amd64 18 guest-start/win.repeat fail REGR. vs.
113359
On Tue, 19 Sep 2017, Rajiv Ranganath wrote:
> We are installing xen in `/opt/` directory. By keeping builds isolated in
> `/opt/` we can test multiple versions of xen during development. In
> production a simliar approach can be used to support multiple versions of
> xen along with a higher level
On Tue, 19 Sep 2017, Rajiv Ranganath wrote:
> From: Rajiv M Ranganath
>
> Signed-off-by: Rajiv Ranganath
Reviewed-by: Stefano Stabellini
> ---
> README.md |1 +
> 1 file changed, 1 insertion(+)
>
> diff
On Tue, 19 Sep 2017, Rajiv Ranganath wrote:
> From: Rajiv M Ranganath
>
> Signed-off-by: Rajiv Ranganath
Acked-by: Stefano Stabellini
> ---
> .circleci/config.yml | 21 +
> 1 file
On Tue, 19 Sep 2017, Rajiv Ranganath wrote:
> From: Rajiv M Ranganath
>
> Signed-off-by: Rajiv Ranganath
Acked-by: Stefano Stabellini
> ---
> build/fedora/source_path.sh |3 +++
> 1 file changed, 3
On Tue, 19 Sep 2017, Rajiv Ranganath wrote:
> From: Rajiv M Ranganath
>
> In order to build stage1-xen we require three components -
>
> 1. Xen
> 2. Qemu
> 3. Rkt
>
> These components are built using scripts in `build/fedora/components/`
> directory. These scripts
On Thu, Sep 21, 2017 at 2:16 PM, Thomas Garnier wrote:
>
> On Thu, Sep 21, 2017 at 8:59 AM, Ingo Molnar wrote:
> >
> > ( Sorry about the delay in answering this. I could blame the delay on the
> > merge
> > window, but in reality I've been
+int pvcalls_front_accept(struct socket *sock, struct socket *newsock, int
flags)
+{
+ struct pvcalls_bedata *bedata;
+ struct sock_mapping *map;
+ struct sock_mapping *map2 = NULL;
+ struct xen_pvcalls_request *req;
+ int notify, req_id, ret, evtchn, nonblock;
+
On Thu, 21 Sep 2017, Jan Beulich wrote:
> >>> On 21.09.17 at 03:12, wrote:
> > On Fri, 1 Sep 2017, Jan Beulich wrote:
> >> --- a/hw/xen/xen_pt_msi.c
> >> +++ b/hw/xen/xen_pt_msi.c
> >> @@ -18,6 +18,11 @@
> >>
> >> #define XEN_PT_AUTO_ASSIGN -1
> >>
> >> +#ifndef
flight 113684 ovmf real [real]
http://logs.test-lab.xenproject.org/osstest/logs/113684/
Regressions :-(
Tests which did not succeed and are blocking,
including tests which could not be run:
build-amd64-xsm 6 xen-buildfail REGR. vs. 113647
build-i386-xsm
On Wed, Sep 20, 2017 at 10:10 AM, Daniel Kiper wrote:
> On Wed, Sep 20, 2017 at 09:59:51AM -0600, Tamas K Lengyel wrote:
>> On Wed, Sep 20, 2017 at 9:46 AM, Jan Beulich wrote:
>> On 20.09.17 at 17:20, wrote:
>> >> On Wed, Sep
On Wed, Sep 20, 2017 at 10:10 AM, Daniel Kiper wrote:
> On Wed, Sep 20, 2017 at 09:59:51AM -0600, Tamas K Lengyel wrote:
>> On Wed, Sep 20, 2017 at 9:46 AM, Jan Beulich wrote:
>> On 20.09.17 at 17:20, wrote:
>> >> On Wed, Sep
On Thu, Sep 21, 2017 at 9:10 AM, Ard Biesheuvel
wrote:
>
> On 21 September 2017 at 08:59, Ingo Molnar wrote:
> >
> > ( Sorry about the delay in answering this. I could blame the delay on the
> > merge
> > window, but in reality I've been
On Thu, Sep 21, 2017 at 8:59 AM, Ingo Molnar wrote:
>
> ( Sorry about the delay in answering this. I could blame the delay on the
> merge
> window, but in reality I've been procrastinating this is due to the
> permanent,
> non-trivial impact PIE has on generated C code. )
flight 113656 xen-unstable real [real]
http://logs.test-lab.xenproject.org/osstest/logs/113656/
Regressions :-(
Tests which did not succeed and are blocking,
including tests which could not be run:
test-amd64-i386-xl-qemuu-win7-amd64 18 guest-start/win.repeat fail REGR. vs.
113387
Thursday, September 21, 2017, 10:39:52 AM, you wrote:
> On Wed, Sep 20, 2017 at 03:50:35PM -0400, Jérôme Oufella wrote:
>> Hi Xen-devel,
>>
>> I'm using PCI pass-through to map a PCIe (intel i210) controller into
>> a HVM domain. The system uses xen-pciback to hide the appropriate PCI
>>
flight 113659 qemu-mainline real [real]
http://logs.test-lab.xenproject.org/osstest/logs/113659/
Failures :-/ but no regressions.
Tests which did not succeed, but are not blocking:
test-armhf-armhf-libvirt-raw 13 saverestore-support-checkfail like 113626
test-armhf-armhf-libvirt-xsm 14
smccc.h provides definitions to construct SMC call function number according
to SMCCC. We don't need multiple definitions for one thing, and definitions
in smccc.h are more generic than ones used in psci.h.
So psci.h will only provide function codes, while whole SMC function
identifier will be
This feature indicates that hypervisor is compatible with ARM
SMC calling convention. Previously hypervisor would inject an
undefined instruction exception if an invalid SMC function were
called or would crash a domain if an invalid HVC function
were invoked.
XENFEAT_ARM_SMCCC_supported feature
PSCI handling code had helper routine that checked calling convention.
It does not needed anymore, because:
- Generic handler checks that 64 bit calls can be made only by
64 bit guests.
- SMCCC requires that 64-bit handler should support both 32 and 64 bit
calls even if they originate
SMCCC (SMC Call Convention) describes how to handle both HVCs and SMCs.
SMCCC states that both HVC and SMC are valid conduits to call to different
firmware functions. Thus, for example, PSCI calls can be made both by
SMC or HVC. Also SMCCC defines function number coding for such calls.
Besides
PSCI is part of HVC/SMC interface, so it should be handled in
appropriate place: `vsmc.c`. This patch moves PSCI handler
calls from `traps.c` to `vsmc.c`. Also it corrects coding
style of the PSCI handler functions.
Older PSCI 0.1 uses SMC function identifiers in range that is
reserved for
Added type xen_uuid_t. This type represents UUID as an array of 16
bytes in big endian format.
Added macro XEN_DEFINE_UUID that constructs UUID in the usual way:
XEN_DEFINE_UUID(0x00112233, 0x4455, 0x6677, 0x8899, 0xaabbccddeeff)
will construct UUID 00112233-4455-6677-8899-aabbccddeeff
Hello all,
v6:
* XEN_DEFINE_UUID() now is in two variants: strict ANSI C and GCC,
more in corresponding patch
* added/reworked helpers that return information about SMCCC service
* fixed bug with compilation of "arm: traps: handle PSCI calls inside `vsmc.c`"
Next patch fixed that bug
This patch defines HSR_XXC_IMM_MASK. It can be used to extract
immediate value for trapped HVC32, HVC64, SMC64, SVC32, SVC64
instructions, as described in the ARM ARM
(ARM DDI 0487B.a pages D7-2270, D7-2272).
Signed-off-by: Volodymyr Babchuk
Acked-by: Julien Grall
Add generic definitions used in ARM SMC call convention.
Those definitions was originaly added to Linux kernel as
include/linux/arm-smccc.h by commit 98dd64f34f47
("ARM: 8478/2: arm/arm64: add arm-smccc")
I extended them and formatted according to XEN coding style. Some
of the macros were
Trapped SMC instruction can fail condition check on ARMv8 architecture
(ARM DDI 0487B.a page D7-2271). So we need to check if condition was meet.
Signed-off-by: Volodymyr Babchuk
Reviewed-by: Julien Grall
---
xen/arch/arm/traps.c | 6 ++
1
There are standard functions set_user_reg() and get_user_reg(). We can
use them in PSCI_SET_RESULT()/PSCI_ARG() macros instead of relying on
CONFIG_ARM_64 definition.
Signed-off-by: Volodymyr Babchuk
Reviewed-by: Julien Grall
---
On 09/15/2017 07:00 PM, Stefano Stabellini wrote:
Send PVCALLS_BIND to the backend. Introduce a new structure, part of
struct sock_mapping, to store information specific to passive sockets.
Introduce a status field to keep track of the status of the passive
socket.
Signed-off-by: Stefano
On 09/21/2017 12:16 PM, Andrew Cooper wrote:
On 21/09/17 17:00, Boris Ostrovsky wrote:
Signed-off-by: Juergen Gross
---
arch/x86/include/asm/xen/page.h | 11 ++-
arch/x86/xen/mmu_pv.c | 4 ++--
2 files changed, 12 insertions(+), 3
On 09/15/2017 07:00 PM, Stefano Stabellini wrote:
Send PVCALLS_CONNECT to the backend. Allocate a new ring and evtchn for
the active socket.
Introduce fields in struct sock_mapping to keep track of active sockets.
Introduce a waitqueue to allow the frontend to wait on data coming from
the
Hi Julien,
On 13.09.17 14:58, Julien Grall wrote:
diff --git a/xen/arch/arm/psci.c b/xen/arch/arm/psci.c
index 34ee97e..be4e8e6 100644
--- a/xen/arch/arm/psci.c
+++ b/xen/arch/arm/psci.c
@@ -31,9 +31,9 @@
* (native-width) function ID.
*/
#ifdef CONFIG_ARM_64
-#define
On Thu, Sep 21, 2017 at 05:47:08PM +0100, Euan Harris wrote:
> xs_check_watch() checks for watch notifications without blocking.
> Together with the binding for xs_fileno(), this makes it possible
> to write event-driven clients in Python.
>
> Signed-off-by: Euan Harris
>
On Thu, Sep 21, 2017 at 05:47:07PM +0100, Euan Harris wrote:
> When a watch fires, xspy_read_watch() checks whether the client has
> registered interest in the path which changed and, if so, returns the
> path and a client-supplied token. The binding for xs_check_watch()
> needs to do the same,
On Thu, Sep 21, 2017 at 05:47:06PM +0100, Euan Harris wrote:
> xs_fileno() returns a file descriptor which receives events when Xenstore
> watches fire. Exposing this in the Python bindings is a prerequisite
> for writing event-driven clients in Python.
>
> Signed-off-by: Euan Harris
flight 113667 ovmf real [real]
http://logs.test-lab.xenproject.org/osstest/logs/113667/
Regressions :-(
Tests which did not succeed and are blocking,
including tests which could not be run:
build-amd64-xsm 6 xen-buildfail REGR. vs. 113647
build-i386-xsm
+
+static inline int get_request(struct pvcalls_bedata *bedata, int *req_id)
+{
+ *req_id = bedata->ring.req_prod_pvt & (RING_SIZE(>ring) - 1);
+ if (RING_FULL(>ring) ||
+ READ_ONCE(bedata->rsp[*req_id].req_id) != PVCALLS_INVALID_ID)
+ return -EAGAIN;
+
Roger Pau Monné writes ("Re: [PATCH v2 04/21] xl: introduce a domain type
option"):
> On Wed, Sep 20, 2017 at 03:50:48PM +0100, Ian Jackson wrote:
> > It would be nice if you did this in a way that meant that a config
> > file which specified both `type="hvm"' and `builder="hvm"' did not
> >
On Wed, Sep 20, 2017 at 03:50:48PM +0100, Ian Jackson wrote:
> Roger Pau Monne writes ("[PATCH v2 04/21] xl: introduce a domain type
> option"):
> > Introduce a new type option to xl configuration files in order to
> > specify the domain type. This supersedes the current builder option.
> ...>
>
Venu Busireddy writes ("Re: [PATCH v3 1/2] libxl: Implement the handler to
handle unrecoverable AER errors"):
> On 2017-08-08 15:33:01 +0100, Wei Liu wrote:
> > I think a bigger question is whether you agree with Ian's comments
> > regarding API design and whether you have more questions?
>
>
xs_check_watch() checks for watch notifications without blocking.
Together with the binding for xs_fileno(), this makes it possible
to write event-driven clients in Python.
Signed-off-by: Euan Harris
Reviewed-by: Wei Liu
---
Expose xs_fileno() and xs_check_watch() to Python. These functions
make it posible to write event-driven Xenstore clients in Python:
#!/usr/bin/env python
import xen.lowlevel.xs
import sys
import errno
from select import select
import time
# Connect to XenStore and set
xs_fileno() returns a file descriptor which receives events when Xenstore
watches fire. Exposing this in the Python bindings is a prerequisite
for writing event-driven clients in Python.
Signed-off-by: Euan Harris
Reviewed-by: Konrad Rzeszutek Wilk
When a watch fires, xspy_read_watch() checks whether the client has
registered interest in the path which changed and, if so, returns the
path and a client-supplied token. The binding for xs_check_watch()
needs to do the same, so this patch extracts the search code into a
separate function.
On 09/21/2017 01:40 PM, Julien Grall wrote:
> Signed-off-by: Julien Grall
> Acked-by: Andrew Cooper
Acked-by: George Dunlap
>
> ---
>
> Cc: George Dunlap
> Cc: Jan Beulich
Hi,
On 21/09/17 16:46, Stefano Stabellini wrote:
On Thu, 21 Sep 2017, Julien Grall wrote:
Hi,
On 20/09/17 00:45, Stefano Stabellini wrote:
diff --git a/xen/include/asm-arm/page.h b/xen/include/asm-arm/page.h
index 30fcfa0778..899fd1801a 100644
--- a/xen/include/asm-arm/page.h
+++
On 09/21/2017 01:40 PM, Julien Grall wrote:
> Some unboxing/boxing can be avoided by using mfn_add(...) instead.
>
> Signed-off-by: Julien Grall
> Acked-by: Andrew Cooper
Reviewed-by: George Dunlap
>
> ---
>
> Cc:
On 09/21/2017 01:40 PM, Julien Grall wrote:
> gfn_aligned is assigned 3 times with the exact same formula. All the
> variables used are not modified, so consolidate in a single assignment
> at the beginning of the function.
>
> Signed-off-by: Julien Grall
> Acked-by: Andrew
Hi,
On 21/09/17 17:28, George Dunlap wrote:
On 09/21/2017 01:40 PM, Julien Grall wrote:
Signed-off-by: Julien Grall
Acked-by: Andrew Cooper
Should probably add something like:
"While we're here, specify 1UL when shifting in a couple of
On 09/21/2017 01:40 PM, Julien Grall wrote:
> Also take the opportunity to:
> - move from 1 << * to 1UL << *.
> - use unsigned when possible
> - move from unsigned int -> unsigned long for some induction
> variables
>
> Signed-off-by: Julien Grall
>
On 09/21/2017 05:28 PM, George Dunlap wrote:
> On 09/21/2017 01:40 PM, Julien Grall wrote:
>> Signed-off-by: Julien Grall
>> Acked-by: Andrew Cooper
>
> Should probably add something like:
>
> "While we're here, specify 1UL when shifting in a
On 09/21/2017 01:40 PM, Julien Grall wrote:
> Signed-off-by: Julien Grall
> Acked-by: Andrew Cooper
Should probably add something like:
"While we're here, specify 1UL when shifting in a couple of cases."
This could be done on check-in.
On 09/21/2017 01:40 PM, Julien Grall wrote:
> Signed-off-by: Julien Grall
> Acked-by: Andrew Cooper
Reviewed-by: George Dunlap
>
> ---
>
> Cc: George Dunlap
> Cc: Jan Beulich
On 09/21/2017 01:40 PM, Julien Grall wrote:
> A lot of the headers are not necessary. At the same time, order them in the
> alphabetical order.
>
> Signed-off-by: Julien Grall
> Acked-by: Andrew Cooper
Acked-by: George Dunlap
branch xen-unstable
xenbranch xen-unstable
job build-amd64-xsm
testid xen-build
Tree: ovmf https://github.com/tianocore/edk2.git
Tree: qemu git://xenbits.xen.org/qemu-xen-traditional.git
Tree: qemuu git://xenbits.xen.org/qemu-xen.git
Tree: xen git://xenbits.xen.org/xen.git
*** Found and
Wei Liu writes ("Re: [PATCH 10/22] xentoolcore_restrict_all: Implement for
libxenforeignmemory"):
> On Tue, Sep 19, 2017 at 12:08:27PM +0100, Ian Jackson wrote:
> > Wei Liu writes ("Re: [PATCH 10/22] xentoolcore_restrict_all: Implement for
> > libxenforeignmemory"):
> > > Sure that's fine.
> >
On 21/09/17 17:00, Boris Ostrovsky wrote:
Signed-off-by: Juergen Gross
---
arch/x86/include/asm/xen/page.h | 11 ++-
arch/x86/xen/mmu_pv.c | 4 ++--
2 files changed, 12 insertions(+), 3 deletions(-)
diff --git a/arch/x86/include/asm/xen/page.h
flight 113669 xen-unstable-smoke real [real]
http://logs.test-lab.xenproject.org/osstest/logs/113669/
Failures :-/ but no regressions.
Tests which did not succeed, but are not blocking:
test-amd64-amd64-libvirt 13 migrate-support-checkfail never pass
test-armhf-armhf-xl
On 21 September 2017 at 08:59, Ingo Molnar wrote:
>
> ( Sorry about the delay in answering this. I could blame the delay on the
> merge
> window, but in reality I've been procrastinating this is due to the
> permanent,
> non-trivial impact PIE has on generated C code. )
>
flight 113655 linux-4.9 real [real]
http://logs.test-lab.xenproject.org/osstest/logs/113655/
Regressions :-(
Tests which did not succeed and are blocking,
including tests which could not be run:
build-armhf-libvirt broken in 113640
build-armhf-pvops
On 09/21/2017 10:41 AM, Juergen Gross wrote:
On 21/09/17 16:14, Boris Ostrovsky wrote:
On 09/21/2017 04:01 AM, Juergen Gross wrote:
Physical addresses on processors supporting 5 level paging can be up to
52 bits wide. For a Xen pv guest running on such a machine those
physical addresses
( Sorry about the delay in answering this. I could blame the delay on the merge
window, but in reality I've been procrastinating this is due to the permanent,
non-trivial impact PIE has on generated C code. )
* Thomas Garnier wrote:
> 1) PIE sometime needs two
Hi,
On 21/09/17 16:46, Stefano Stabellini wrote:
> On Thu, 21 Sep 2017, Julien Grall wrote:
>> Hi,
>>
>> On 20/09/17 00:45, Stefano Stabellini wrote:
diff --git a/xen/include/asm-arm/page.h b/xen/include/asm-arm/page.h
index 30fcfa0778..899fd1801a 100644
---
On Thu, 21 Sep 2017, Julien Grall wrote:
> Hi,
>
> On 20/09/17 00:45, Stefano Stabellini wrote:
> > > diff --git a/xen/include/asm-arm/page.h b/xen/include/asm-arm/page.h
> > > index 30fcfa0778..899fd1801a 100644
> > > --- a/xen/include/asm-arm/page.h
> > > +++ b/xen/include/asm-arm/page.h
> > >
On Thu, Sep 21, 2017 at 01:40:33PM +0100, Julien Grall wrote:
> Signed-off-by: Julien Grall
> Acked-by: Andrew Cooper
>
Reviewed-by: Wei Liu
___
Xen-devel mailing list
On Thu, Sep 21, 2017 at 01:40:34PM +0100, Julien Grall wrote:
> - Switch the return type to bool
> - Remove the parameter p2m_query_t q as it is not used
>
> Signed-off-by: Julien Grall
> Acked-by: Andrew Cooper
Reviewed-by: Wei Liu
On Thu, Sep 21, 2017 at 01:40:32PM +0100, Julien Grall wrote:
> Signed-off-by: Julien Grall
> Acked-by: Andrew Cooper
>
Reviewed-by: Wei Liu
___
Xen-devel mailing list
On Thu, Sep 21, 2017 at 01:40:31PM +0100, Julien Grall wrote:
> At the same time make the array gfns const has it is not modified within
> the function.
>
> Signed-off-by: Julien Grall
> Acked-by: Andrew Cooper
Reviewed-by: Wei Liu
On Thu, Sep 21, 2017 at 01:40:30PM +0100, Julien Grall wrote:
> Signed-off-by: Julien Grall
> Acked-by: Andrew Cooper
Reviewed-by: Wei Liu
___
Xen-devel mailing list
On Thu, Sep 21, 2017 at 01:40:29PM +0100, Julien Grall wrote:
> Signed-off-by: Julien Grall
> Acked-by: Andrew Cooper
Reviewed-by: Wei Liu
___
Xen-devel mailing list
On Thu, Sep 21, 2017 at 01:40:28PM +0100, Julien Grall wrote:
> Signed-off-by: Julien Grall
> Acked-by: Andrew Cooper
> Acked-by: Tamas K Lengyel
>
Reviewed-by: Wei Liu
On Thu, Sep 21, 2017 at 01:40:27PM +0100, Julien Grall wrote:
> Signed-off-by: Julien Grall
> Acked-by: Andrew Cooper
> Reviewed-by: Kevin Tian
>
Reviewed-by: Wei Liu
On Thu, Sep 21, 2017 at 01:40:26PM +0100, Julien Grall wrote:
> Signed-off-by: Julien Grall
> Acked-by: Andrew Cooper
I wonder how gfn_lock work with the new time without any change, but it
appears gfn_lock ignores gfn completely. :-)
Hi,
On 20/09/17 00:45, Stefano Stabellini wrote:
diff --git a/xen/include/asm-arm/page.h b/xen/include/asm-arm/page.h
index 30fcfa0778..899fd1801a 100644
--- a/xen/include/asm-arm/page.h
+++ b/xen/include/asm-arm/page.h
@@ -26,14 +26,14 @@
* LPAE entry; the 8-bit fields are packed
>>> On 21.09.17 at 16:58, wrote:
> Do you foresee potentially issue of temporarily modifying permissions of
> a mapping?
It's generally not a good idea imo, but perhaps it's fine here. I
assume the page permissions can't be adversely affected despite
their hard coding in
On Thu, Sep 21, 2017 at 7:03 AM, Jan Beulich wrote:
On 20.09.17 at 22:57, wrote:
>> --- a/xen/common/efi/boot.c
>> +++ b/xen/common/efi/boot.c
>> @@ -1226,9 +1226,13 @@ efi_start(EFI_HANDLE ImageHandle, EFI_SYSTEM_TABLE
>> *SystemTable)
>>
Hi Jan,
On 21/09/17 13:16, Jan Beulich wrote:
On 21.09.17 at 00:31, wrote:
@@ -43,7 +46,29 @@ int arch_livepatch_quiesce(void)
return -ENOMEM;
}
-return 0;
+if ( nfuncs )
+{
+unsigned long va = (unsigned long)func;
+unsigned
On Thu, Sep 21, 2017 at 01:40:25PM +0100, Julien Grall wrote:
> Some unboxing/boxing can be avoided by using mfn_add(...) instead.
>
> Signed-off-by: Julien Grall
> Acked-by: Andrew Cooper
Reviewed-by: Wei Liu
On Thu, Sep 21, 2017 at 01:40:24PM +0100, Julien Grall wrote:
> gfn_aligned is assigned 3 times with the exact same formula. All the
> variables used are not modified, so consolidate in a single assignment
> at the beginning of the function.
>
> Signed-off-by: Julien Grall
On Thu, Sep 21, 2017 at 01:40:23PM +0100, Julien Grall wrote:
> Also take the opportunity to:
> - move from 1 << * to 1UL << *.
> - use unsigned when possible
> - move from unsigned int -> unsigned long for some induction
> variables
>
> Signed-off-by: Julien Grall
On Thu, Sep 21, 2017 at 01:40:22PM +0100, Julien Grall wrote:
> Signed-off-by: Julien Grall
> Acked-by: Andrew Cooper
Reviewed-by: Wei Liu
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On Thu, Sep 21, 2017 at 01:40:20PM +0100, Julien Grall wrote:
> A lot of the headers are not necessary. At the same time, order them in the
> alphabetical order.
>
> Signed-off-by: Julien Grall
> Acked-by: Andrew Cooper
Reviewed-by: Wei Liu
On Thu, Sep 21, 2017 at 01:40:21PM +0100, Julien Grall wrote:
> Signed-off-by: Julien Grall
> Acked-by: Andrew Cooper
>
Reviewed-by: Wei Liu
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On 20/09/17 21:26, Volodymyr Babchuk wrote:
On 20.09.17 23:02, Julien Grall wrote:
On 20/09/2017 19:11, Volodymyr Babchuk wrote:
On 20.09.17 20:21, Julien Grall wrote:
On 19/09/17 22:44, Volodymyr Babchuk wrote:
Hi Julien,
Hi Volodymyr,
On 13.09.17 14:11, Julien Grall wrote:
On Thu, Sep 21, 2017 at 12:13:55PM +0100, Wei Liu wrote:
> On Thu, Sep 21, 2017 at 12:08:04PM +0100, Roger Pau Monné wrote:
> > On Wed, Sep 20, 2017 at 05:18:16PM +0100, Jennifer Herbert wrote:
> > > On 20/09/17 11:20, Roger Pau Monné wrote:
> > > > On Tue, Sep 19, 2017 at 07:06:26PM +0100,
On Thu, Sep 21, 2017 at 02:53:54PM +0100, Wei Liu wrote:
> On Tue, Sep 19, 2017 at 04:29:32PM +0100, Roger Pau Monne wrote:
> > This function allows to iterate over a rangeset while removing the
> > processed regions.
> >
> > It will be used by the following patches in order to store memory
> >
On 21/09/17 16:14, Boris Ostrovsky wrote:
>
>
> On 09/21/2017 04:01 AM, Juergen Gross wrote:
>> Physical addresses on processors supporting 5 level paging can be up to
>> 52 bits wide. For a Xen pv guest running on such a machine those
>> physical addresses have to be supported in order to be
On Wed, Sep 20, 2017 at 03:50:27PM -0400, Boris Ostrovsky wrote:
> It's a leftover from PVHv1 days.
>
> Signed-off-by: Boris Ostrovsky
Reviewed-by: Roger Pau Monné
Thanks, Roger.
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Xen-devel
On 09/21/2017 04:01 AM, Juergen Gross wrote:
Physical addresses on processors supporting 5 level paging can be up to
52 bits wide. For a Xen pv guest running on such a machine those
physical addresses have to be supported in order to be able to use any
memory on the machine even if the guest
On Tue, Sep 19, 2017 at 04:29:32PM +0100, Roger Pau Monne wrote:
> This function allows to iterate over a rangeset while removing the
> processed regions.
>
> It will be used by the following patches in order to store memory
> regions in rangesets, and remove them while iterating.
>
>
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