> From: Jan Beulich [mailto:jbeul...@suse.com]
> Sent: Friday, December 09, 2016 5:43 PM
ing
>
> >>> On 09.12.16 at 04:17, wrote:
> > IA32_PERF_GLOBAL_STATUS.OvfUncore (MSR 38EH, bit[61]) is always 0 and
> > writing 1 to IA32_PERF_GLOBAL_OVF_CTRL.ClrOvfUncore (MSR 390H, bit[61])
> > signals #GP.
>>> On 12.12.16 at 09:06, wrote:
>> >>> On 12.12.16 at 07:51, wrote:
>> > By the way, I think another place may need to do some modify as well.
>> >
>> > @@ -868,7 +868,7 @@ static int core2_vpmu_do_interrupt(struct
>> > cpu_user_regs *regs)
>> > if ( is_pmc_quirk )
>> > ha
> >>> On 12.12.16 at 07:51, wrote:
> > By the way, I think another place may need to do some modify as well.
> >
> > @@ -868,7 +868,7 @@ static int core2_vpmu_do_interrupt(struct cpu_user_regs
> > *regs)
> > if ( is_pmc_quirk )
> > handle_pmc_quirk(msr_content);
> >
>>> On 12.12.16 at 07:51, wrote:
> By the way, I think another place may need to do some modify as well.
>
> @@ -868,7 +868,7 @@ static int core2_vpmu_do_interrupt(struct cpu_user_regs
> *regs)
> if ( is_pmc_quirk )
> handle_pmc_quirk(msr_content);
> core2_vpmu_cxt
> On 12/08/2016 10:17 PM, Luwei Kang wrote:
> > IA32_PERF_GLOBAL_STATUS.OvfUncore (MSR 38EH, bit[61]) is always 0 and
> > writing 1 to IA32_PERF_GLOBAL_OVF_CTRL.ClrOvfUncore (MSR 390H,
> > bit[61]) signals #GP.
> > Reference "Intel Xeon Phi Procssor x200 Product Family", document
> > number 334646-
On 12/08/2016 10:17 PM, Luwei Kang wrote:
> IA32_PERF_GLOBAL_STATUS.OvfUncore (MSR 38EH, bit[61]) is always 0 and
> writing 1 to IA32_PERF_GLOBAL_OVF_CTRL.ClrOvfUncore (MSR 390H, bit[61])
> signals #GP.
> Reference "Intel Xeon Phi Procssor x200 Product Family", document
> number 334646-008.
>
> Sig
>>> On 09.12.16 at 04:17, wrote:
> IA32_PERF_GLOBAL_STATUS.OvfUncore (MSR 38EH, bit[61]) is always 0 and
> writing 1 to IA32_PERF_GLOBAL_OVF_CTRL.ClrOvfUncore (MSR 390H, bit[61])
> signals #GP.
> Reference "Intel Xeon Phi Procssor x200 Product Family", document
> number 334646-008.
I can see this
IA32_PERF_GLOBAL_STATUS.OvfUncore (MSR 38EH, bit[61]) is always 0 and
writing 1 to IA32_PERF_GLOBAL_OVF_CTRL.ClrOvfUncore (MSR 390H, bit[61])
signals #GP.
Reference "Intel Xeon Phi Procssor x200 Product Family", document
number 334646-008.
Signed-off-by: Luwei Kang
---
xen/arch/x86/cpu/vpmu_inte
