On 23/03/17 18:06, Andre Przywara wrote:
Hi,
Hi Andre,
On 06/02/17 17:43, Julien Grall wrote:
Hi,
On 30/01/17 18:31, Andre Przywara wrote:
+int gicv3_its_init(struct host_its *hw_its)
+{
+uint64_t reg;
+int i;
+
+hw_its->its_base = ioremap_nocache(hw_its->addr, hw_its->size);
Hi,
On 06/02/17 17:43, Julien Grall wrote:
> Hi,
>
> On 30/01/17 18:31, Andre Przywara wrote:
>> +int gicv3_its_init(struct host_its *hw_its)
>> +{
>> +uint64_t reg;
>> +int i;
>> +
>> +hw_its->its_base = ioremap_nocache(hw_its->addr, hw_its->size);
>> +if ( !hw_its->its_base )
>>
Hi Shanker,
thanks for having a look.
On 24/02/17 19:29, Shanker Donthineni wrote:
> Hi Andre
>
>
> On 02/16/2017 01:03 PM, Shanker Donthineni wrote:
>> Hi Andre,
>>
>>
>> On 01/30/2017 12:31 PM, Andre Przywara wrote:
>>> Each ITS maps a pair of a DeviceID (usually the PCI b/d/f triplet) and
>>>
Hi Andre
On 02/16/2017 01:03 PM, Shanker Donthineni wrote:
Hi Andre,
On 01/30/2017 12:31 PM, Andre Przywara wrote:
Each ITS maps a pair of a DeviceID (usually the PCI b/d/f triplet) and
an EventID (the MSI payload or interrupt ID) to a pair of LPI number
and collection ID, which points to th
Hi Andre,
On 01/30/2017 12:31 PM, Andre Przywara wrote:
Each ITS maps a pair of a DeviceID (usually the PCI b/d/f triplet) and
an EventID (the MSI payload or interrupt ID) to a pair of LPI number
and collection ID, which points to the target CPU.
This mapping is stored in the device and collect
Hi Andre,
On 01/30/2017 12:31 PM, Andre Przywara wrote:
Each ITS maps a pair of a DeviceID (usually the PCI b/d/f triplet) and
an EventID (the MSI payload or interrupt ID) to a pair of LPI number
and collection ID, which points to the target CPU.
This mapping is stored in the device and collect
On Mon, 6 Feb 2017, Julien Grall wrote:
> > +static uint64_t encode_phys_addr(paddr_t addr, int page_bits)
> > +{
> > +uint64_t ret;
> > +
> > +if ( page_bits < 16 )
> > +return (uint64_t)addr & GENMASK(47, page_bits);
> > +
> > +ret = addr & GENMASK(47, 16);
> > +return ret
On Mon, 30 Jan 2017, Andre Przywara wrote:
> Each ITS maps a pair of a DeviceID (usually the PCI b/d/f triplet) and
> an EventID (the MSI payload or interrupt ID) to a pair of LPI number
> and collection ID, which points to the target CPU.
> This mapping is stored in the device and collection table
Hi,
On 30/01/17 18:31, Andre Przywara wrote:
+int gicv3_its_init(struct host_its *hw_its)
+{
+uint64_t reg;
+int i;
+
+hw_its->its_base = ioremap_nocache(hw_its->addr, hw_its->size);
+if ( !hw_its->its_base )
+return -ENOMEM;
+
+for ( i = 0; i < GITS_BASER_NR_REGS; i+
On 30/01/17 18:31, Andre Przywara wrote:
diff --git a/xen/arch/arm/gic-v3.c b/xen/arch/arm/gic-v3.c
index fcb86c8..440c079 100644
--- a/xen/arch/arm/gic-v3.c
+++ b/xen/arch/arm/gic-v3.c
@@ -29,6 +29,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -1563,6 +15
Hi Andre,
On 30/01/17 18:31, Andre Przywara wrote:
Each ITS maps a pair of a DeviceID (usually the PCI b/d/f triplet) and
an EventID (the MSI payload or interrupt ID) to a pair of LPI number
and collection ID, which points to the target CPU.
This mapping is stored in the device and collection ta
Each ITS maps a pair of a DeviceID (usually the PCI b/d/f triplet) and
an EventID (the MSI payload or interrupt ID) to a pair of LPI number
and collection ID, which points to the target CPU.
This mapping is stored in the device and collection tables, which software
has to provide for the ITS to use
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