>>> On 24.11.16 at 18:22, wrote:
> On 24/11/16 15:25, Jan Beulich wrote:
> On 23.11.16 at 16:38, wrote:
>>> +case x86_seg_tr:
>>> +ASSERT(reg->attr.fields.p); /* Usable. */
>>> +ASSERT(!reg->attr.fields.s); /* System segment. */
>>> +
On 24/11/16 15:25, Jan Beulich wrote:
On 23.11.16 at 16:38, wrote:
>> +case x86_seg_tr:
>> +ASSERT(reg->attr.fields.p); /* Usable. */
>> +ASSERT(!reg->attr.fields.s); /* System segment. */
>> +ASSERT(!(reg->sel & 0x4));
>>> On 23.11.16 at 16:38, wrote:
> +case x86_seg_tr:
> +ASSERT(reg->attr.fields.p); /* Usable. */
> +ASSERT(!reg->attr.fields.s); /* System segment. */
> +ASSERT(!(reg->sel & 0x4)); /* !TI. */
> +ASSERT(reg->att
> From: Andrew Cooper [mailto:andrew.coop...@citrix.com]
> Sent: Wednesday, November 23, 2016 11:39 PM
>
> Intel VT-x and AMD SVM provide access to the full segment descriptor cache via
> fields in the VMCB/VMCS. However, the bits which are actually checked by
> hardware and preserved across vmen
On 23/11/16 19:41, Boris Ostrovsky wrote:
> On 11/23/2016 02:28 PM, Andrew Cooper wrote:
>>> SVM requires attributes of any NULL segment to be zero.
>> Where is this claim made? Vol2 recommends that the VMM clear all
>> attributes, but the wording of the previous paragraph suggests that the
>> att
On 11/23/2016 02:28 PM, Andrew Cooper wrote:
>
>> SVM requires attributes of any NULL segment to be zero.
> Where is this claim made? Vol2 recommends that the VMM clear all
> attributes, but the wording of the previous paragraph suggests that the
> attributes would be ignored in this case. The %
On 23/11/16 19:01, Boris Ostrovsky wrote:
> On 11/23/2016 10:38 AM, Andrew Cooper wrote:
>> Intel VT-x and AMD SVM provide access to the full segment descriptor cache
>> via
>> fields in the VMCB/VMCS. However, the bits which are actually checked by
>> hardware and preserved across vmentry/exit a
On 11/23/2016 10:38 AM, Andrew Cooper wrote:
> Intel VT-x and AMD SVM provide access to the full segment descriptor cache via
> fields in the VMCB/VMCS. However, the bits which are actually checked by
> hardware and preserved across vmentry/exit are inconsistent, and the vendor
> accessor function
Intel VT-x and AMD SVM provide access to the full segment descriptor cache via
fields in the VMCB/VMCS. However, the bits which are actually checked by
hardware and preserved across vmentry/exit are inconsistent, and the vendor
accessor functions perform inconsistent modification to the raw values
