Hi Andrew,
On 16/10/17 15:38, Andrew Cooper wrote:
* x86 PV and ARM dom0's must not clear _VPF_down from v->pause_flags until
all state is actually set up. As it currently stands, d0v0 is eligible for
scheduling before its registers have been set. This is latent as we also
hold a
On Mon, Oct 16, 2017 at 03:38:03PM +0100, Andrew Cooper wrote:
> * x86 PV and ARM dom0's must not clear _VPF_down from v->pause_flags until
>all state is actually set up. As it currently stands, d0v0 is eligible for
>scheduling before its registers have been set. This is latent as we als
>>> On 17.10.17 at 12:38, wrote:
> On 16/10/17 17:21, Jan Beulich wrote:
> On 16.10.17 at 18:07, wrote:
>>> On 16/10/17 16:41, Jan Beulich wrote:
>>> On 16.10.17 at 16:38, wrote:
> --- a/xen/arch/x86/hvm/dom0_build.c
> +++ b/xen/arch/x86/hvm/dom0_build.c
> @@ -614,6 +614,7
On 16/10/17 17:21, Jan Beulich wrote:
On 16.10.17 at 18:07, wrote:
>> On 16/10/17 16:41, Jan Beulich wrote:
>>> >>> On 16.10.17 at 16:38, wrote:
--- a/xen/arch/x86/hvm/dom0_build.c
+++ b/xen/arch/x86/hvm/dom0_build.c
@@ -614,6 +614,7 @@ static int __init pvh_setup_cpus(struct
On Mon, 16 Oct 2017, Andrew Cooper wrote:
> * x86 PV and ARM dom0's must not clear _VPF_down from v->pause_flags until
>all state is actually set up. As it currently stands, d0v0 is eligible for
>scheduling before its registers have been set. This is latent as we also
>hold a systemc
On 16/10/17 16:51, Roger Pau Monné wrote:
> On Mon, Oct 16, 2017 at 03:38:03PM +0100, Andrew Cooper wrote:
>> * x86 PV and ARM dom0's must not clear _VPF_down from v->pause_flags until
>>all state is actually set up. As it currently stands, d0v0 is eligible
>> for
>>scheduling before its
>>> On 16.10.17 at 18:07, wrote:
> On 16/10/17 16:41, Jan Beulich wrote:
>> >>> On 16.10.17 at 16:38, wrote:
>>> --- a/xen/arch/x86/hvm/dom0_build.c
>>> +++ b/xen/arch/x86/hvm/dom0_build.c
>>> @@ -614,6 +614,7 @@ static int __init pvh_setup_cpus(struct domain *d,
>>> paddr_t entry,
>>>
>>>
On 16/10/17 16:39, Jan Beulich wrote:
On 16.10.17 at 16:49, wrote:
>> On 16/10/17 15:44, Wei Liu wrote:
>>> On Mon, Oct 16, 2017 at 03:38:03PM +0100, Andrew Cooper wrote:
* x86 PV and ARM dom0's must not clear _VPF_down from v->pause_flags until
all state is actually set up. As
On 16/10/17 16:41, Jan Beulich wrote:
> >>> On 16.10.17 at 16:38, wrote:
>> --- a/xen/arch/x86/hvm/dom0_build.c
>> +++ b/xen/arch/x86/hvm/dom0_build.c
>> @@ -614,6 +614,7 @@ static int __init pvh_setup_cpus(struct domain *d,
>> paddr_t entry,
>>
>> update_domain_wallclock_time(d);
>>
>>
On Mon, Oct 16, 2017 at 03:38:03PM +0100, Andrew Cooper wrote:
> * x86 PV and ARM dom0's must not clear _VPF_down from v->pause_flags until
>all state is actually set up. As it currently stands, d0v0 is eligible for
>scheduling before its registers have been set. This is latent as we als
>>> On 16.10.17 at 16:38, wrote:
> --- a/xen/arch/x86/hvm/dom0_build.c
> +++ b/xen/arch/x86/hvm/dom0_build.c
> @@ -614,6 +614,7 @@ static int __init pvh_setup_cpus(struct domain *d,
> paddr_t entry,
>
> update_domain_wallclock_time(d);
>
> +v->is_initialised = 1;
> clear_bit(_V
>>> On 16.10.17 at 16:49, wrote:
> On 16/10/17 15:44, Wei Liu wrote:
>> On Mon, Oct 16, 2017 at 03:38:03PM +0100, Andrew Cooper wrote:
>>> * x86 PV and ARM dom0's must not clear _VPF_down from v->pause_flags until
>>>all state is actually set up. As it currently stands, d0v0 is eligible
> f
On Mon, Oct 16, 2017 at 03:49:54PM +0100, Andrew Cooper wrote:
> On 16/10/17 15:44, Wei Liu wrote:
> > On Mon, Oct 16, 2017 at 03:38:03PM +0100, Andrew Cooper wrote:
> >> * x86 PV and ARM dom0's must not clear _VPF_down from v->pause_flags until
> >>all state is actually set up. As it current
On Mon, Oct 16, 2017 at 03:38:03PM +0100, Andrew Cooper wrote:
> * x86 PV and ARM dom0's must not clear _VPF_down from v->pause_flags until
>all state is actually set up. As it currently stands, d0v0 is eligible for
>scheduling before its registers have been set. This is latent as we als
* x86 PV and ARM dom0's must not clear _VPF_down from v->pause_flags until
all state is actually set up. As it currently stands, d0v0 is eligible for
scheduling before its registers have been set. This is latent as we also
hold a systemcontroller pause reference at the time which preven
On 16/10/17 15:44, Wei Liu wrote:
> On Mon, Oct 16, 2017 at 03:38:03PM +0100, Andrew Cooper wrote:
>> * x86 PV and ARM dom0's must not clear _VPF_down from v->pause_flags until
>>all state is actually set up. As it currently stands, d0v0 is eligible
>> for
>>scheduling before its registe
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