Re: [Xen-devel] [PATCH v2] x86/PV: fix/generalize guest nul selector handling

2017-10-04 Thread Andrew Cooper
On 28/09/17 09:41, Jan Beulich wrote: > Segment bases (and limits) aren't being cleared by the loading of a nul > selector into a segment register on AMD CPUs. Therefore, if an > outgoing vCPU has a non-zero base in FS or GS and the subsequent > incoming vCPU has a non-zero but nul selector in the

Re: [Xen-devel] [PATCH v2] x86/PV: fix/generalize guest nul selector handling

2017-10-04 Thread Jan Beulich
>>> On 29.09.17 at 17:17, wrote: > On Thu, Sep 28, 2017 at 08:41:28AM +, Jan Beulich wrote: >> --- a/xen/arch/x86/domain.c >> +++ b/xen/arch/x86/domain.c >> @@ -1237,6 +1237,18 @@ arch_do_vcpu_op( >> return rc; >> } >> >> +/* >> + * Loading a nul selector does

Re: [Xen-devel] [PATCH v2] x86/PV: fix/generalize guest nul selector handling

2017-09-29 Thread Andrew Cooper
On 29/09/17 16:17, Roger Pau Monné wrote: > On Thu, Sep 28, 2017 at 08:41:28AM +, Jan Beulich wrote: >> Segment bases (and limits) aren't being cleared by the loading of a nul >> selector into a segment register on AMD CPUs. Therefore, if an >> outgoing vCPU has a non-zero base in FS or GS and

Re: [Xen-devel] [PATCH v2] x86/PV: fix/generalize guest nul selector handling

2017-09-29 Thread Roger Pau Monné
On Thu, Sep 28, 2017 at 08:41:28AM +, Jan Beulich wrote: > Segment bases (and limits) aren't being cleared by the loading of a nul > selector into a segment register on AMD CPUs. Therefore, if an > outgoing vCPU has a non-zero base in FS or GS and the subsequent > incoming vCPU has a non-zero

[Xen-devel] [PATCH v2] x86/PV: fix/generalize guest nul selector handling

2017-09-28 Thread Jan Beulich
Segment bases (and limits) aren't being cleared by the loading of a nul selector into a segment register on AMD CPUs. Therefore, if an outgoing vCPU has a non-zero base in FS or GS and the subsequent incoming vCPU has a non-zero but nul selector in the respective register(s), the selector value(s)