Hi Jan,
On 24/03/16 11:28, Jan Beulich wrote:
On 24.03.16 at 12:12, wrote:
(CC committers)
On 24/03/16 10:54, Stefano Stabellini wrote:
On Wed, 23 Mar 2016, Julien Grall wrote:
Hi Stefano,
On 22/02/16 17:38, Stefano Stabellini wrote:
On Fri, 15 Jan 2016, Ian
>>> On 24.03.16 at 12:12, wrote:
> (CC committers)
>
> On 24/03/16 10:54, Stefano Stabellini wrote:
>> On Wed, 23 Mar 2016, Julien Grall wrote:
>>> Hi Stefano,
>>>
>>> On 22/02/16 17:38, Stefano Stabellini wrote:
On Fri, 15 Jan 2016, Ian Campbell wrote:
I
(CC committers)
On 24/03/16 10:54, Stefano Stabellini wrote:
On Wed, 23 Mar 2016, Julien Grall wrote:
Hi Stefano,
On 22/02/16 17:38, Stefano Stabellini wrote:
On Fri, 15 Jan 2016, Ian Campbell wrote:
I read the patch and looks good to me. You can add my
Reviewed-by: Stefano Stabellini
On Wed, 23 Mar 2016, Julien Grall wrote:
> Hi Stefano,
>
> On 22/02/16 17:38, Stefano Stabellini wrote:
> > On Fri, 15 Jan 2016, Ian Campbell wrote:
> >
> > I read the patch and looks good to me. You can add my
> >
> > Reviewed-by: Stefano Stabellini
> >
> >
Hi Stefano,
On 22/02/16 17:38, Stefano Stabellini wrote:
On Fri, 15 Jan 2016, Ian Campbell wrote:
I read the patch and looks good to me. You can add my
Reviewed-by: Stefano Stabellini
I have a couple of minor comments, which you can ignore or address as
you
On Fri, 15 Jan 2016, Ian Campbell wrote:
> From: Julien Grall
>
> On AArch64, encoding 31 for an R in the HSR is used to represent
> either {w,x}sp or {w,x}zr (See C1.2.4 in ARM DDI 0486A.d) depending on
> how the register field is interpreted by the instruction.
>
>
From: Julien Grall
On AArch64, encoding 31 for an R in the HSR is used to represent
either {w,x}sp or {w,x}zr (See C1.2.4 in ARM DDI 0486A.d) depending on
how the register field is interpreted by the instruction.
All the instructions trapped by Xen (either via a sysreg