On Fri, Aug 04, 2017 at 09:48:59AM -0600, Jan Beulich wrote:
> >> Anthony PERARD 08/04/17 1:38 PM >>>
> >On Thu, Aug 03, 2017 at 09:21:57AM -0600, Jan Beulich wrote:
> >> >>> Anthony PERARD 07/18/17 7:12 PM >>>
> >> >@@ -818,6 +840,7 @@
>> Anthony PERARD 08/04/17 1:38 PM >>>
>On Thu, Aug 03, 2017 at 09:21:57AM -0600, Jan Beulich wrote:
>> >>> Anthony PERARD 07/18/17 7:12 PM >>>
>> >@@ -818,6 +840,7 @@ static void vlapic_reg_write(struct vcpu *v,
>> >if (
On Thu, Aug 03, 2017 at 09:21:57AM -0600, Jan Beulich wrote:
> >>> Anthony PERARD 07/18/17 7:12 PM >>>
> >@@ -678,18 +679,29 @@ static void vlapic_tdt_pt_cb(struct vcpu *v, void
> >*data)
> >static void vlapic_update_timer(struct vlapic *vlapic, uint32_t lvtt);
> >{
>
>>> Anthony PERARD 07/18/17 7:12 PM >>>
>@@ -678,18 +679,29 @@ static void vlapic_tdt_pt_cb(struct vcpu *v, void *data)
>static void vlapic_update_timer(struct vlapic *vlapic, uint32_t lvtt);
>{
>uint64_t period;
>-uint64_t delta;
>-bool is_periodic;
>+
If we take TSC-deadline mode timer out of the picture, the Intel SDM
does not say that the timer is disable when the timer mode is change,
either from one-shot to periodic or vice versa.
After this patch, the timer is no longer disarmed on change of mode, so
the counter (TMCCT) keeps counting